Virtex 4, how do I generate 100khz clock

I am new to FPGAs and Xilinx Virtex 4. How do I create a 100khz clock signal?

Reply to
jim
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The very first step is to figure out the required accuracy and stability. High accuracy or stability requires an external crystal oscillator and probably a divider. Low requirements can be satisfied with an external RC circut. Peter Alfke

Reply to
Peter Alfke

jim,

With a 100 KHz clock source.

OK, seriously, the DCM can only divide an input clock by 15 (or 16, I forget) on the CLKDV output, and since the minimum input CLKIN for this feature is 24 MHz, that will not get you down to 100 KHz.

The alternative is to use the CLB DFF to construct a divide by N (whatever you need) counter, and put the clock you have into the BUFG clock net (from an input pint), and take the clock out of the MSB of the counter (divider).

External clock sources which are crystal based are easily obtained for less than a few dollars. These have frequencies from 5 MHz to 100 MHz at fairly low cost. Above 100 MHz, the oscillators are more exotic, and cost more.

In is not recommended to try to attach a bare crystal to IO pins to construct an oscillator.

Austin

Reply to
Austin Lesea

Get a circuit like this one :-

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Tune it to about 198kHz, and throw away the low pass filter bit that drives the headphones. Take it to Droitwich in the UK. You'll easily receive Radio

4 long wave, there's a 500kW transmitter there. Connect signal to Virtex 4. Use a flip flop in said FPGA to divide the 198kHz carrier clock by 2. This gives you 99kHz, near enough, I expect.

Here's a link.

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Looks like you're 18 years too late, the frequency changed to 198 kHz from the perfect 200kHz in 1989.

HTH, Syms. :-)

Reply to
Symon

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