asynchronous circuit design

I use many instances of that minimal asynchronous circuit called a D-flop :)

-- Mike Treseler

Have you looked at Handshake Solutions?

I'm sure there are other such tools around too. However, I'm not aware of *any* asynchronous design tools that are truly mainstream.

For FPGAs, the structure of the devices and the behaviour of their place-and-route tools effectively makes asynchronous design intractable for ordinary mortals.

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how

sanju,

Somebody is using asynchronous design?

Wow. I thought it died (yet again) awhile ago now.

I think when the famous asynchronous ARM chip was built synchronously and was better in every possible way (size: smaller, power: less, etc.), that it effectively killed asynchronous design (again).

I have yet to see a single case where asynchronous design has any advantages.

In the small (phase detectors, D flip flop, clock switches, FIFO, and so on), asynchronous design must be used (somewhere). But it is usually done by one expert (and only that one expert is allowed to do any asynchronous design).

Much more popular is "Globally asynchronous, locally synchronous" or GALS approach to design, where groups of synchronous logics communicate with others using asynchronous handshake protocols.

No need for any new tools.

Austin

There is a chapter called Level-Mode Sequential Circuits in Introduction to Switching Theory & Logical Design Frederick J. Hill Gerald R. Peterson Third Edition Copyright 1968, 1974, 1981 John Wiley & Sons, Inc.

Perhaps a Google Search will pick up related, newer references.

-Newman, a synchronous guy ... not asynchronous

I've read an article about it in 1999 [1] and it sounds interesting, but I don't know, if it is still used. If you use well known technics, like dual-rail signalling [2,3] or the Muller C gate [3], looks like you don't need to be an "expert".

One advantage which isn't obvious and I remember from article [1] was, that the power consumption is lower, because you don't have to distribute a global clock signal all over the chip, but you need only locally coupled components.

[1] [2] [3]

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Yes, ( but not much in your FPGA world )

Take a look at :

See above.

I'd agree that Async+FPGA is not a good combination (sic).

That moves into areas where the FPGA vendors have not tested their tools, and it is hard enough to get the tools 'settled down' on areas the vendors supposedly DO test !!

FPGAs already have large silicon resources cast for SYNC designs. Thus whilst you could, in theory, do some research projects on async, in FPGA, for final production in other ASIC flows, it would not be trivial.

-jg

Check out

Balsa HDL for async design

also

Async FPGA, hardware is async

Google "async digital circuits" find other Universities doing similar research

Agree with the other previous post. Current FPGAs not suited for async, global clock trees already exist, might as well use them. You will utilize more logic elments to implement the async logic. If your goal is to save power you may save power (correct dynamic power should be lower) but it will be at the cost of more logic usage, issues verifying timing (depending what async architecture you use), PAR (tools may not understand it is async?).

Paper on using current FPGA tool flow for async

If the goal is to learn async circuit design, you can implement async in standard Verilog or VHDL and/or try Balsa.

Couple free books online on the subject as well.

Good luck and lets us know how it goes.