SPI communication problem with Si3215 & AT91SAM7SE256

Easy enough to test. Put a pull up resistor at the end of the clk, data in,and data out signals and see if the problem clears up. I try to keep my SPI and I2C lines as a single trace with a terminating pull up after the last device, just as standard practice, and have never had a problem with any devices. I would rather have a longer trace length, especially at such a low clock rate, than to have a fan out to multiple signal paths.

Hi WangoTango,

I tried your solution by placing pull-up(2.2K) on SCLK, MOSI and MISO but does not help anyway.

There are total 8 SPI Slave devices, all on the same board, and each device needs a separate chip select.

And as the MCU has only 4 encoded chip select outputs, i am using an external decoder to decode them to 16 individual chip selects. Only 8 of them are used.

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4 MHz is not fast, I've seen a board with 25 MHz without problems with a AT91 microcontroller and a wire length of more than 5 cm (with the SSC interface, which is SPI on steroids). There was no termination or some pullup resistors. But you could try to use a series resistor, something like 20 ohm, for reducing ringing.

Ok, just some dumb ideas, I'm sorry if you have already checked it, but your question on the maximum input current suggests that you are a beginner in embedded electronics.

This could be some border case. Are you sure, that you are using the right SPI mode? Did you measure with scope SCL and SDA and verify it with the timing diagrams in the datasheet? E.g. if the chip samples SDA with rising SCL edge and you change with rising edge, too, then maybe sometimes it doesn't work anymore, if the capacity on the SCL is higher when you test it with a scope. You have to generate the signal on the other edge than it is sampled.

Usually the inputs are high impedance inputs, if it is a CMOS chip and not an old TTL chip. Maybe this means, a digital pin can sink 10 mA max, if it is switched to output.

Are you sure your multiplexer generates the right chip select signals, e.g. active low? BTW: If you have 16 IO spare pins on your microcontroller, you can connect all chipselects to your microcontroller and generate it in software.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Hi Frank,

Yes, I have observed the clock and data signals of SPI on Oscilloscope and yes I am using the correct mode. The MCU changes the data on Leading edge (Falling Edge) of the Clock and Slaves sample it on Trailing edge(Rising Edge). Same way the slaves change the data on leading edge and MCU samples it on trailing edge.

I can generate the chip select signals from software but as in our new board model the number of slaves on SPI is going to increase upto 24, so better to generate from external hardware.

And BTW, how does my question on the maximum input current suggest that I am a beginner in embedded electronics?

Thanks Faiyaz

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Probably because CMOS inputs draw very little current, even taking into accoutn the input capacitance.

The 4MHz clock is not an issue, it is the rise an fall times that cause problems due to reflections. For some interesting reading have a look at the Blckfin SPI documentation.

It could be that using the HC125 is improving performand because it has slightly slower rise times that the CPU.

As Frank says, try series resitors in the SCLK and MOSI signals. I would suggest values more like 100 ohms, but it may be worth experimenting.

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Because the current you mentioned (10 mA IIRC) must be in the "absolute maximum ratings" section of the datasheet. That means it is the maximum current allowed to flow in the pin before it goes up in smoke. Such a current will only flow if the input voltage is higher than the supply voltage. It is most likely the maximum rating for the input clamping diodes.

For the actual input current under normal conditions, look in the operational data section of the datasheet. There may be something like "input leakage current", probably in the uA range. This is the static current the input will draw (or supply, a lot of times the figure is

+/-). But as another poster said, the current through the input capacitance will likely be higher at your clock frequency than the static input current..

And I think you can drop the 'embedded' from your question above. Based on that question, you seem to be a beginner in electronics. ;-)

When driving a large number of chips with a single clock, there are likely to be a lot of reflections, which may mess up your signal. You may also have problems with the large capacitive load on the signal. Both problems should be less of a problem if you lower the clock frequency, so that's worth a try.

Both problems can be simulated and/or measured with a scope. If you use a scope, watch the input capacitance of your probe an make sure the ground connection is really short. Use the ground ring at the probe tip to touch a ground very close to the signal you are measuring. Just using the probe's alligator clip ground wire will most likely make you see ringing signals where there are none.

--
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

A mushroom cloud has no silver lining.

Hi RockyG,

I applied your suggestion of using series resistors on Clock & MOSI signals. I used 50 Ohm series resistors on both signals and i can now observe that the problem of Ringing & Overshoot is significantly reduced.

I also tried reducing the SPI clock upto 500 KHz.

But the problem remains there as it is...

& Thanks Stef and RockyG for the info regarding the digital inputs and CMOS charactersitics. I just wanted to gain the knowledge that is why I asked..

Thanks Faiyaz

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