Picoblaze VHDL Code Block diagram

I am interested in adding a "busy" signal to the Input/Ouptut port of the Picoblaze. This will allow me to add a Wishbone wrapper to the picoblaze and allow me to used some free wishbone cores from Opencores.org.

Since the picoblaze is written using xilinx primatives the VHDL code is a little hard to follow. On to my question:

Has anyone put together a block diagram of the internal signal connections of the picoblaze?

The Xilinx documantation I've seen doesn't "pictorially" show the internal signal connections.

I'm willing to look through the code and put together a diagram, but if someone else has done it and could save me some time... great!

Thanks, Eric Holland snipped-for-privacy@hotmail.com

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Might be a better place to start, assuming you can read Verilog.

Regards, Allan

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Allan Herriman

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