News info below. Automotive customers tend to be tough on reliability, and on standard supply voltages.
Of interest in this release are
0.13u/150MHz core, but they manage to deliver 5V I/O, ADCs etc [ FPGA vendors could learn from this ]
Comment on error correcting FLASH
Not mentioned here, but also noted, is the trend to require a Vpp or PGM enable pin, on Automotive FLASH parts. Seems to be a concern about shipping a part that MIGHT be able to re-program its own flash ?
- jg
Motorola news item : "Based on 0.13-micron design rules, the MPC5554 chip operates at speeds of 50 to 150MHz. Though the design rules are advanced, Motorola made the part so that its I/O and ADC will run at 5V, which automakers often prefer.
The company also said it designed the flash memory to be more reliable by adding error correcting code. The flash is built to retain data for
20 years and withstand 100,000 read/erase cycles. The first MPC5554 will include 2 Mbytes of flash, and the company is planning to come out with a 4Mbyte version next year, Cornyn said. "
I think your last comment is unfair. I'm sure their 5V I/O doesn't even begin to approach the performance levels that you can obtain from the programmable I/O in recent FPGAs.
There's nothing impossible about 5V I/O using .13u (or 90 nm). It just takes more processing steps, which means more $$$ to build the chip. On top of that, the structures that would result may be good for 5V I/O, but not for 840 Mbps LVDS...
I believe the "features" available in recent FPGAs is the result of market forces at work.
Five volts would have been nice for some incremental respins of older products. Instead I had to level translate (using an IDT device) which was $$$, real estate etc. I definitely would have liked it to be supported in the FPGA.
Don't get me wrong. As a standard bus interface IP developer (PCI, PCI-X, and now PCI Express...) I like 5V I/O even more than the next guy. I'd love to be able to directly support
5V PCI on newer Xilinx parts without external components.
What I was trying to point out is that the economic/market reality of 5V support on newer FPGA devices has resulted in a tradeoff: faster, low voltage I/O and less costly devices at the expense of 5V I/O support.
I believe every major programmable logic manufacturer has made this tradeoff. It isn't Xilinx trying to alienate users of 5V logic. If someone can show me a commercial FPGA at .15u or below that has real 5V I/O support, I'll eat humble pie.
Like you pointed out, those who need a lot of 5V I/O end up paying for it, either by using older parts (more $/logic) or external (more $) components such as level translators. It is the unfortunate cost of designing with I/O signaling levels that are no longer mainstream.
I'd agree with that, if you are looking at a 5V application then high speed LVDS I/O probably doesn't get you very far...
For a general purpose FPGA, with general purpose programmable I/O, you need this on every pin... While the end user makes a selection via the bitstream, the actual hardware has to be capable of handling all possible configurations.
On recent devices, 5V I/O is gone... I would not be surprised if it's the same issue all over again with 3.3V in a few years.
As I had mentioned, it is possible to build a device to support
5V I/O. That device will cost more for everyone, even if they are not using 5V I/O. Those I/O will also be slower. I believe few people would buy these parts, due to the higher cost and lower performance.
There are other approaches -- things like dedicated banks of I/O just for a specific purpose. Xilinx uses this for the gigabit serial transceivers in V2pro. One could do something similar but for a bank of 5V I/O. For 5V I/O, it would still make the devices more expensive.
I do not believe making general purpose devices more expensive to cater to a declining market is a good business decision. I think, for better or worse, we're all being swept along by the tide of economics.
If there's "not enough market" I doubt anyone trying to make money is going to address it. If there were a significant market, but there were technical hurdles, I am sure people here, and at other FPGA vendors, would be researching a way to cash in on it.
In the near future, I don't think the FPGA will be a direct drop in replacement for a controller with tons of 5V I/O.
The vision of a programmable system is that the entire system goes into the FPGA. What might have been 5V signals between all the modules are now low voltage signals running over the internal FPGA routing, because almost everything is iniside the FPGA. There will still be things outside. But most of those that use a large number of I/O (large memories, etc...) are no longer designed with 5V I/0. A quick survey of Micron, Cypress, and IDT websites will confirm this.
For smaller RAMs (things like a 6116, etc...) those can be implemented in the FPGA block memory. So the need for these things with high pincount 5V I/O goes away...
I'm not denying that you will need 5V I/O. Just that you probably don't need much, unless you're doing a legacy design, and in that case you might anticipate having to pay for a feature that is not in "mainstream" use anymore. That's how it appears to me, at least in the FPGA market...
You do get the speed for these new I/O voltages - for new designs this is great. I was wondering if Xilinx et al considers respins a design win as well? I've been presented with the situation that if we can upgrade performance/function on an existing 5V design the benifits are faster market and lower test risk. I believe the major concern for a 5V I/O sink/source pin is capacitance regardless of the speed it's used at. I'd like to see 5V I/O, or an acceptable work-around while still meeting the requirements of the other speeds.
Not true. Some of the more esoteric IOs are already 'blocked' Users could live with not having 5V IO on every single IO, jus like they live with not having 840MHz SerDes on every IO.
Depends on where you look, and why. On embedded controllers, 5V is actually making a comeback. Lattices' very newest CPLDs, added 5V tolerant IOs.
On chip regulators are also appearing, as other vendors look at ways to expand the use-ability of the shrink silicon.
Give the customers some hard numbers, and let them decide for themselves :)
I see Hynix have just released a high voltage 0.18u process, that targets LCD display drivers (so high voltage here means
40-50V region )
Some numbers ? XX cents per pin ?
They are already. Wider Vcc range devices are appearing, you just have to look for them (they are not appearing in FPGA markets first). Narrow/lowered/restricted Vcc devices have been replaced by better engineered, wider Vcc ones.
There was an interesting earlier thread that touched on leakage failure modes in higher IO on the finest processes.
I see we have a difference of opinion. I'm not going to try to change your mind, only answer the additional questions you posed:
There are no Xilinx devices like this. With the exception of the gigabit serial I/O, all I/O pins are the same.
There are some vendors that have banking rules like you have described, but even so, those banks don't support 5V I/O.
I am looking specifically at the FPGA market.
Most vendors have limited resources, and so make intelligent guesses about price/feature tradeoffs. The market is wide open for someone do exactly what you suggest.
I don't have this information. If I did, I'm sure my employer would not be pleased if I were to share it. However, I do know that the expense is considerable:
Additional mask sets.
Additional processing steps.
Cost of lost general purpose I/O.
Cost of a low volume, "novelty" product, including software, support, and documentation.
It would be more expensive. I don't know how much. Time will tell if FPGA vendors think this is a good return on investment.
Quite understood. I am looking from a designers viewpoint, across many markets, and asking 'why' wrt a specific feature.
Accepted - perhaps one more, maybe none with the right cleverness. Note this mask would not be 0.13u, nor full die area.
Yes, and it also requires that the foundry qualify the process, which requires their customers indicate they need it.
This may come sooner than you think. I see foundries are now offering 110nm process as a 'back fill' between the 130nm and 90nm processes. Seems the customers are not rushing to 90nm quite as fast as they hoped - so a significant mindset change is occuring where smallest/fastest is no longer the sole target on the radar.
Not sure they are mutually exclusive. An IC designer could exclude it on some specialist high speed IO.
The other markets releasing 'wide supply' ICs do not think they are "novelty" products - quite the reverse. Their intention is to have one die cover as many customers as practical, and reduce the part number proliferation, as well as extend the 'design life' of a given die.
There are LOTS of benefits along the whole supply chain.
LOGIC has now moved to 1.65-5.5V Vcc specs after some market failures with lower/narrower offerings. uC are following, with the better ones now doing 1.8-5.5V, or 2.0-5.5V - some uC and CPLD have on-die regulators. When you see the curves, you can appreciate the 1.8-5.5V was not easy, and not without effort or some silicon cost.
Besides Wide Vcc, commercial temp spec releases are being dropped in favour of industrial (or wider) 'as standard'.
See rickmans post, covers the trade-offs designers face and the reasons for device selection, nicely.
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