Large power planes vs. power islands vs. slits for decoupling

I think they focus solely on the Powersupply, and forget about things like ground bounce ( that does not appear in S21 )

- so from an attenuation viewpoint, dual splits would work, and could maybe help if that section of the FPGA was internal only, and had no Pin-drive signals [rare, but not impossible]

I was pondering going even further, by taking a device along these lines, and assembling into a cavity in the PCB (object is to remove the vias), but I think that would have problems with getting solder paste into the cavity ?

Of course, the ideal is to have Xilinx put this into the BGA carrier .

-jg

Hi Jim, Right. I wonder if some of those interposer materials might offer a solution in the future? Some sort of bypass circuit in between the BGA and the PCB somehow? Dunno, Syms.

Hmm, yes, the largest one is close to die-sized, at ~17x15mm, (a monster, and also 2.5mm thick), but for that you get wideband low-milliohms impedances, and 300uF/1000uF, so imagine a couple of BGA layers made of this stuff....

- probably worth more to customers than putting the boot-prom into the package, measured in practical PCB area cost, and EMC/RFI gains....

Interesting this was driven by the games industry, which also gives us the Cell CPU..

In the short term, I think one of these/rail on the opposite side of the PCB, would be a usefull step, that only needs the Chip & FPGA vendors to talk to each other.

Of course, Xilinx's volumes are far less exciting than PS3.

It's a little hard to decode the exact footprint/keepouts of these.

-jg

at:-

plane.http://www.chemi-con.co.jp/english/support_e/proadlizer_e.html

:-

All, Austin's description of the NEC Proadlizer is fairly accurate. It is a transmission line filter. The really wilde S21 insertion loss curves occur when the device interrupts both Vcc and Vss ( gnd ). But it is still quite impressive interrupting just Vcc. When we decouple power to a device or a node, we are concerned with two issues: S21 insertion loss which measures the ability of a device to isolate noise, and Z22 which is the impedance that the filter presents to the load. While Proadlizers with plane slits are killer at S21, they are quite pedestrian at Z22 exhibiting about 200pH mounted with a ton of vias. If you were to try and use these for Virtex 4 or 5 in the 672 pin or smaller packages, or Altera parts prior to Stratix III that do not have internal bypass caps on an I/O rail you would set yourself up for a world of hurt. Using a Proadlizer with larger V4 or V5 or Altera Stratix III where the chips do have substantial bypass caps in the package can work to isolate the local bypass from the plane.

Why do we want to bypass large devices from the planes? Because by doing so PROPERLY, we can: reduce EMI propagation to the board edges, raise the SRF of the power cavity to put it well above the cross-over frequency of power distribution low pass in the package, and isolate big hungry parts from smaller parts and each other. In the PS3 application, those mighty ASICs have a lot of bypass under the lid.

the PCB do all the work. The PCB just becomes a low frequency power distribution network. Since Sony isn't asking the PCB to distribute high frequency, using the Proadlizers to isolate noise is an effective way to limit EMI propagation. That allows meeting FCC with thicker dielectric in the power planes of the PCB.

The last I checked, Proadlizers were in the dollars range / part. But the capacitor industry is very competitive and this may have improved.

X2Y's ( I consult for X2Y ) can also be used to effect high frequency isolation by feeding Vcc through the G1/G2 connection and grounding the A and B connections. We have seen EMI improvements of 50dB with carefully designed etch and a pair of 1206 size X2Ys.

On the load side of things ( your chip ) you need to pay attention to the local impedance versus frequency, Z22. Problems occur if the impedance is too high. At audio frequencies this is usually a resonance problem between the voltage regulator and the bulk bypass network. Above 1MHz it is either from too much inductance and/or a resonance.

Regards,

Steve.

Hi Steve, Firstly, thanks for your post. I lurk on the SI-list (posting is a pain with all those 'out-of-office' replies) which is how I found your stuff on X2Y. The paragraph of yours I've quoted above explains to me what's going on inside a PS3. For a while I was worrying that I'd missed a big trick with my FPGA board designs. If FPGA manufacturers follow this lead of putting even more bypassing on the BGA carrier, and I guess that soon they will have no choice, then the PCB power distribution requirements will become a little less rigorous. Thanks again, Symon.

wrote

Interesting. Here is a proadlizer test showing this on pages 16-17:

It looks like the proadlizer is not that good in decoupling mode though

200pH is still pretty good for 1200µF and that a few low ESL caps are probably needed anyway.

Marc

Which cap geometries are used for in-package decoupling?

According to the following paper (see page 34), they use (used?) 8 pins IDC caps:

X2Y and 10 pins IDC caps are much better now so maybe they changed.

Marc

Symon, you are welcome. An out of office junk filter is mandatory for SI-List sanity.

Intel has been doing what you mention for a long time. The cut-off frequency between the PCB and package is down in the low MHz, and falling. For all of those other chips, the keys to good decoupling are: low inductance, low inductance, and low inductance. That is why I like X2Y's so much and consult for X2Y. Six vias with one X2Y will get you 100pH at the surface + 4-5pH / mil for plunge down to the power cavity. Only IDC caps come close with similar numbers for eight vias. Resonance management is a matter of managing phase. That too means getting low inductance.

I have long been fascinated with the Proadlizers but have never found a situation where I felt they were the best answer. They are (or were ) pricey, big and need a lot of vias. I have always found I could synthesize a cheaper solution with cheaper capacitors, sometimes a little creative etch, and in the very rare instance a little iron.

The FPGA guys have an interesting set of trade-offs to resolve. They tend to use power pins for signal return path as well as power distribution. They also don't get to choose return path of things like DDR2 memory, which is Vss for data and Vccio for address / control. As edge rates continue to push upwards, this gets trickier to manage.

Regards,

Steve.

I use gmane.org to lurk on SI-List - it allows you to use a proper newsreader, which makes life a lot nicer...

--
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

My first thought on your previous post on split power planes, and considering them as transmission lines, is that you can distribute the effect of the clock transitions back to the power supply.

If you have multiple FPGAs on a board, all clocked at the same time, but with different length low impedance transmission lines to the power supply, (bypass capacitors), you distribute the effect of those capacitors. Then again, you should be able to get a similar effect with different clock delays.

If you have a split ground plane it would seem that the signal lines should go around, and not cross the split.

-- glen

The signal will go where the copper is which is over the ground plane split. The return current for that signal will follow it's copper which is in the ground or power plane so it will be forced around the split. This separates the signal current from it's return current which causes a nice big radiating loop....bad for EMI if the edge rate on that signal is single digit nanoseconds.

Kevin Jennings

What I meant was the the copper should follow the ground plane, such that the signal does go that way. It says signal lines, so I don't see how you would read it any other way.

-- glen