If you are only seeing zeroes on TDO, how about checking all of your connections from the cable to the target system? Don't forget to power the cable, too
JTAG chains are notoriously problem areas so let start with some basics.
Try and keep the TMS, TDI, TCK runs together. If get a big difference between particularly TCK and the others you can get into setup and hold issues.
If you programming cable is home grown watch out for the edge rates coming out of the cable. They may be very fast and causing reflections. Add series resistors if this is the problem.
Different devices have different JTAG voltages for operation. Driving at
2.5V may be marginal on a 3.3V JTAG. Driving at 3.3V may put too much current, through protection diode, into a 2.5V JTAG device.
To help in all this IMPACT has a debug mode where you can waggle signals at will and follow operation with an oscilloscpe.
What cable are you using?
John Adair Enterpoint Ltd. - Home of Raggesdtone1. The Cheap Spartan-3 Development Board.
I got it to work! Strange solution. By mounting a CPLD on my board and routing FPGA_TDO into CPLD_TDI and connecting the JTAG cable to: FPGA_TDI og CPLD_TDO
Maby the CPLD is more tolerent? My JTAG system is running 2.5V
If you are using a Xilinx cable, you need to make certain that the board voltage is connected to the cable to ensure that the drive levels are suitably adjusted.
If you are using some other cable, I suspect that the cable drive level would be to blame.
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