IEEE 1284 Core for Xilinx

This is a slave device? Do you need the full-scale 1284 protocol for device recognition, or just the handshaking part of it? I have built a set of devices that control CNC machine axes using the 1284 handshaking (read encoder position, compute new velocity, send velocity to DAC or step pulse rate generator).

I get a transfer rate of about 800 nS per byte. I put an address counter in the device, so consecutive registers can be loaded (or read) without sending a new address.

I found the most useful info on the protocol in the data sheets for the SMC

37C665 series of chips. Note that the chips in motherboards do NOT follow the Microsoft document on signal timing. SMC chips send the strobes at the same time as the data. UMC chips send the strobes BEFORE the data! (The standard shows the strobes being delayed by an unstated amount.)

The hardware to control this is trivial. It fits on one small page of schematics, and can be implemented in small CPLDs, as well as FPGAs.

Jon

what you mean you cant afford ISE (full release) there is no difference if you use ISE or ISE Webpack in this case.

a full IEEE1284 peripheral core is available from japanese site it did show the windows parallel port enumaration screen i.e. the parallel port device is recognized as plug and play and displays manufacturer info.

unfortunatly I cant find the link any more :( it wasnt of interest for me so I forgot.

but for simple handshaking its not hard to hand-craft it from scratch

antti

there are 2 links to IEEE1284 vhdl for xilinx :) found it

google: IEEE1284 FPGA :)

antti

Is there one with the IEEE 1284 Core VHDL that is in english?

Regards,

I

of

my

I poked around a while and found the VHD file, which seems readable. I haven't tried to UNDERSTAND it yet, however - that is different.

Jon

good, come alone and you all will learn japanese as god as I ;)

I dont understand nothing in japanese. And this is how I read japanese HDL/FPGA pages:

1 check pictures 2 check all hyperlinks, even if page is japanese the línks may have english page names :) 3 download all HDL files and all archive files, check whats inside

the link what you found seems to be full IEEE1284 peripheral core with plug and play support (there is screenshot of the plug and play enumeration so I assume it is working and verified on FPGA)

the design does synthesise out of box for Xilinx XST 256 Slices or 60% of XC95 144 for Actel APA075 its 25%

the design is larger than commercial IEEE1284 cores, but it has plug and play enumaration built in (what you can easily comment out if needed)

antti

What part of it can be commented out. Does the PC care that it is a plug and play connection?

Will it fit on a CPLD 95xxx?

Regards,

James

I found that it did synthesise into an XC95144, however is does not fit into the device use the fitter of the ISE.

Regards,

James

look out our Chameleon POD based Parallel port. We have designed on it 1284 EPP controller, it works fine, and is fully tested in your ' OCDemon Raven JTAG ' configuration. Our EPP controller core is very small and can be mapped on a 64 Flip-Flops device (ex: Xilinx Coolrunner XCR3064XL or other CPLD)

Contact me if you want pur EPP controller core, I can give you the VHDL source if you need.

Laurent Amontec Team

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with plug and play and debug disabled it fits into XC9572 with ISE

antti

What parts are the plug and play?

Why is there a separate IEEE1284_IN and out port? Couldn't that be the same

8bit bidirectional port?

Also,

I asked if I could get the EPP VHDL that you mentioned, but I had to change my email address because of the current virus going around was swamping my incoming messages. My new email is snipped-for-privacy@williams-eng.com

Regards,

James

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