PIC MSSP module in I2C mode

- R
- Ralf Hildebrandt
  
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posted
19 years ago

Wed, Jun 16, 2004 11:39 AM

Hi all!

The Microchip PIC16F87XA has got a MSSP module. Bits SSPM(3 downto 0) in SSPCON register configure the mode of the module. For I2C operation the following options are available:

1111 = I2C slave, 10bit addressing, with START/STOP interrupts 1110 = I2C slave, 7bit addressing, with START/STOP interrupts 1011 = I2C firmware controlled master mode (Slave idle) 1000 = I2C master mode 0111 = I2C slave, 10bit addressing 0110 = I2C slave, 7bit addressing

I am troubled, whith the "firmware controlled master mode". What does this mode do? Where can I find some helpful documentation about it?

There is only one sentence about this mode in the manual - subsection "Master mode" (9.4.6 in the data sheet): "In Firmware Controlled Master mode, user conducts all I2C bus operations based on START and STOP bit conditions."

I have searched the website of Microchip and did a research in the web and newsgroups via google, but did not found any helpful desciptions about this mode. Seems to be, that nobody uses this mode...

I have some ideas, what this mode could be, but I am not shure: Lets assume, that in this mode the I2C module is disabled (SSPSR does not shift, WCOL, SSPOV, BF (and the other flags) are not touched .. and so on...). The only part of the I2C module, that is enabled is the START and the STOP detector. Both trigger an interrupt. All I2C bus operations are done through software, manipulating PORTC. --- But if one realizes a I2C master doing so, START/STOP interrupts are not nessecary, because the I2C master drives START/STOP. It could be helpful, if one whishes to realize a I2C slave in software, but this way this mode would not be called a "master mode". So I am a little bit confused about the basic function of this mode.

Thanks for help. Ralf

- T
- Thad Smith
  
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posted
19 years ago

Wed, Jun 16, 2004 3:41 PM

I don't have a direct answer, but have found Microchip to be responsive in the past for technical questions, at least with regard to MPLAB. I suggest contacting them via email or using a forum on their web site.

Thad

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- Gary Kato
  
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posted
19 years ago

Wed, Jun 16, 2004 9:37 PM

Actually, start and stop bit detection in Master mode is useful when there can be multiple masters. A simple example:

On Reset: (assumes that all I2C devices are reset at the same time) I2Cbus = FREE;

On Start condition detection: I2Cbus = BUSY;

On Stop condition detection: I2Cbus = FREE;

When you try to start an I2C transaction: while (I2Cbus != FREE) ; // start transaction

I'm not taking bus collisions into account here.

If it's possible for only your device to be reset, you can't assume the bus is free on reset since another I2C Master might be in the middle of a transaction. In this case, you'd have to flag the bus status as UNKNOWN and watch the SCL line for a certain amount of time to see if it is toggling as well as using Start and Stop condition detection. If SCL toggled in that time period, the bus is BUSY; if it was IDLE all that time, then the bus is FREE.