i2c slave does not acknowlege


im trying to use the i2c opensource IPCore to control my CMOS image sensor through i2c interface. The sensor can only work as a i2c slave. it does not contain any pullups internally for scl/sda, so i add them with in the FPGA ( spartan 3 ). i dont use any external resistors for this. Is this acceptable?

when monitored by the chipScope logic analyzer, it seems like the sensor does not acknowlege when i write the device address Plus write bit. im sure the device address i sent is correct. the sensor im using is KAC-9630 from Kodak. Please let me know if someone can figure this out.

Thank You. CMOS

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Most I2C pullups are in the region of 2k ohm or so (maybe less). That's far lower than the pullups inside most Xilinx parts (typically 25k -


There are excellent app notes at Philips (the inventors of I2C) on this.

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Xilinx do not guarantee a minimum pullup current. They used to (IIRC the value was 25uA) but this led to problems with designers thinking they could use the pullups in lieu of resistors on their boards and running into problems with leakage current and poor risetimes.

You should read the I2C specification. It will make it pretty clear you're doing something wrong. (In general, you should read specifications *before* you design your system.)

Chipscope is good for looking at what is going on inside the chip. I suggest you use an oscilloscope instead.

Regards, Allan

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Maybe it's a timing issue. Some I2C devices are slower than others. Does your chipScope analyzer show any drop in the clk signal at all? Does the Kodak part have any address pins that augment the address? Good luck, I know how frustrating the I2C bus can be.

Brad Smallridge aivision.com

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Brad Smallridge

The other option could just be to scan the bus - do a read from every address to see whether you get any ACK at all. This could help if you have a bug in the addressing - I know I've had some confusion before when reading datasheets for certain parts.

The other point of course is just checking with an oscilloscope, to check whether you've got something that's not being pulled up/down hard enough, and hence not registering.


Reply to
Jeremy Stringer

hi, thanx for the advice. i 'll try both of these. however in the KODAK spec it mentions its addresss clearly as 1000100. and in the analyzer i see the same being transfered to the device with LSB set to 0 to indicate a Write. all the properties are normal, i.e sda changes only when the scl is low, start bit is correct. just before the ACK clock pulse, the sda goes high and stays there continuously. So i dont see any stop condition in the waveform. i thought this is because slave does not acknowlege the master.


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CMOS a =E9crit:

Hi Your SDA and SCL ports should be bidir (I haven't checked OC's design so I assume they are). Use ChipScope to monitor SDA & SCL *inputs* to the FPGA, not its outputs. This will show you what's going on on the actual bus lines, not what the FPGA drives out. (this is an alternative to the use of an oscilloscope :o)


Reply to
Nicolas Matringe

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