Microcontroller with I2C AND robust clock stretching?

This is a slightly unusual request. Normally, clock stretch was used for the simplest bit level slaves, with SW layers that needed to slow down the master. - see the Philips LPC7xx series for bit-level i2c examples.

Once you have Byte level i2c, then clock stretch is less relevent, and most such systems ( eg Serial EE memories), work by ACK/NACK to signal busy. That way, you do not lock up the whole i2c bus with a slow system. Most modern uC have no problems keeping up with byte level i2c transport, even up to ~ 1MHz.

-jg

The 16F876 PIC would only clock stretch on a read. The updated 16F876A clock stretches on both read and writes.

Assuming you are not using SM Bus: If the Slave does not ACK you can not assume reception and need to retransmit until you get the ACK. You can also try to have the slave force the clock low after the byte is received. The Master will be forced to wait.

Thanks guys.

Regarding comments that the Master should check for ACK with each byte, doesn't an ACK by the slave merely tell the master that the byte was received? However, if the slave microcontroller's isr does not run in timely manner (for example, if other isrs are running), then the only way to inhibit the master would be to stretch the clock.