Hi I synthesised my verilog code in synplify. And do the P&R in quartusII. When I did not config some of the pins FPGA ran correctly.But when I config these pins,it went wrong result! I can believe the pins did not affect the internal function! The board freq meet the timing report of quartusII. I don't know why. The fpga is Altera 20k200e
Thanks and Regards