You would implement this the same way as any other external module
declare it like this
( .(your internal signal to be connected), .(), .(), .90 )
Where is the name of the library module you wish to use.
Note that the angle brackets '' are placeholders that would not appear. The periods before the signal names are required for Verilog, and all the parenthesis are also required.
Cheers
PeteS
hello i need some helps... i have an altera FPGA and an external FIFO (IDT72241) connected with the FPGA.
now i want integrate the external FIFO in the FPGA using lpm_fifo or lpm_fifo_dc altera_lpm library.
someone can suggest me how to modify the library to make work it at the same way of the IDT72241.
pS: i use verilog descriptive language
thank you so much and sorry for not my perfect english This message was sent using the sci.electronics.basics web interface on
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