Multiple clocks design

Hi all,

I've got a VHDL design for Stratix Altera FPGA with several differents clocks (5).

There's a clock generator which is configured by the user. So some parts in design can work at different clock frequency.

How can I P&R under Quartus 5.1 for these differents clocks frequency. I have synthesize it with one clock.

Do I synthesise with all the differents clocks (each design with each clocks) and test which design works better ?

Or synthesize the module where the clock frequency can change and put the 5 architectures and select the good architecture for the desired clock used by "soft" VHDL ?

Do you have ideas for these multi-clocks design ?


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