Hi all,
In Xilinx Virtex world, each element in the logic cell has a name and can be explicitly instanstiated, such as "muxcy_l" etc... Is there a way to do the same thing for the Altera Stratix device?
In Xilinx data sheet all those cell elements has a name associated with it in the figure, so it made it easy to know which element to call up from the virtex library in the synthesis tool. I can't find any reference in the Altera document however, so just by inspecting the stratix hdl technology/timing model library I can't be sure which carry mux is which in the logic element.
Would someone who had hand massage the code with technology elements share their method or the reference material from the vendor?
Thanks!
Jon