The original post expired before I answered, so the original question is included below.
Hi Jon,
Sorry I didn't follow up to your post -- I was on vacation, and now google won't let me post a follow up (guess it expired).
I've posted a follow-up now. This data is inside the QUIP documentation. Go to
The information on how to directly instantiate Stratix or Cyclone logic cells in any legal mode is in the stratix_wysuser_doc.pdf document. You can instatitate these primitives directly in verilog or VHDL files.
Regards,
Vaughn Altera
=========================================================== From: J.Ho ( snipped-for-privacy@yahoo.com) Subject: How to explicitly call out cell elements in Altera Stratix? This is the only article in this thread View: Original Format Newsgroups: comp.arch.fpga Date: 2003-12-05 17:31:30 PST
Hi all,
In Xilinx Virtex world, each element in the logic cell has a name and can be explicitly instanstiated, such as "muxcy_l" etc... Is there a way to do the same thing for the Altera Stratix device?
In Xilinx data sheet all those cell elements has a name associated with it in the figure, so it made it easy to know which element to call up from the virtex library in the synthesis tool. I can't find any reference in the Altera document however, so just by inspecting the stratix hdl technology/timing model library I can't be sure which carry mux is which in the logic element.
Would someone who had hand massage the code with technology elements share their method or the reference material from the vendor?
Thanks!
Jon