Hello all I have just downloaded the WebPack and am terribly surprised: I can't find how to instantiate standard IP cores such as memories. CoreGen isn't part of WebPack, so how are users supposed to use memories and so on?
Nicolas
ISE WebPack and IPs (no CoreGen)Xilinx
Aug 03, 2004
1 Replies
on?
by direct instantioting ??
of start the schematics editor, place the memory primitive and later look at the vhdl/verilog core generated for the schematics
antti
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