glitching AND gate

I don't know what you are trying to do but that description almost sounds like what Achronix was doing when they started out. You'll observe, that despite their name, they eventually switched to synchronous logic.

When push came to shove the async logic aspect was not as important as it was to just make fast FPGAs which Achronix did by getting a leg up on the major FPGA players by using Intel's 22 nm FINFET technology.

The part I don't get is that Intel has bought Altera, so the fab service contract with Achronix is now competing with another Intel arm (pun intended).

I'm not familiar with Achronix but I know of one other asynchronous FPGA project that ended up being flushed. Certainly this line of argument is similar to a friend's who keeps pointing out to me that, while async was more common back in the day, the entire industry has gone synchronous since sometime back in the 1960s and so there must be a reason. Yep, probably.

What I'm thinking of is more along the lines of the Balsa synthesis system from University of Manchester.

OK, as long as you know what you're getting into. If you want to publish papers, that's great, but if you have something to deliver on a deadline, I'd avoid this whole line of thought...

Hi,

Am Sonntag, 23. April 2017 15:37:50 UTC+2 schrieb David Bridgham:

About the LUT itself a lot told you in this thread. But be aware that your verilog code will be optimized by synthesis tool. Usually synthesis tools don't care about glitch free result, so you need to ensure your final result is glitch free.

regards Thomas