Gated Clock Problems

My window for arguing has past ... I no longer feel like it. Mike

But, this doesn't answer the problem he is trying to, which is which signal arrives first. If the two songlas both have edges within the same synchronous system clock, you get no answer, ie. they both changed dufing the same sample interval. Entirely depending on what he is really trying to do here, an occasional metastable hangup may be perfectly fine, as long as you get the before/after decision 99% of the time. By the way, you can probably ONLY do this in Xilinx parts, many other architectures won't let you connect FF clocks to combinatorial or non-clock nets without contortions. For pure digital, synchronous systems, that is fine, for these special cases, Xilinx saves the day. (It also allows the neophyte to dig himself a BIG hole!)

Jon

Actually, the metastability window on modern FPGA flip-flops is INCREDIBLY small, probably less than 10 ps on most modern architectures.

Jon

If you want to actually see metastability, it is bets to start with a slow technology, like the 74HC74. Build a clock circuit that pulses the clock input at 1 MHz, say, then arrange a circuit that can adjust the state change of the D input + or - of the clock by a couple ns. Make it a very small range, because even on these slow FFs the sampling window is really small. When you hit that timing window, the output will not change from 1 to 0 abruptly, but will statistically give a % of 1's and

0's. With a good analog scope or a fast digital phosphor scope, you will see some changes that are later than the time-clock-to-output. Those were the metastable events, where the FF did not settle on one state immediately. If you try to do this with an FPGA FF, you will spend all day with exotic lab gear trying to get one event.

Jon

Fail!

Hi Jon, Thanks for your post, but sorry, but that last statement is bollocks. It's easy to get metastable events in an FPGA. X, A, L or otherwise. Email Xilinx and ask about Virtex 4 fifos. Or search through this newsgroup's archive. Or do the maths. HTH., Syms.

Hi Jon, Sorry about that reply, re-reading it, I sound a little aggressive, dunno what came over me. Anyway, have a quick shufty at this.

It's Peter from Xilinx's metastability experiments. Perhaps it will change your mind? Best regards, Syms.

You could try a *really* slow technology like latching relays. Metastability resolution times are long, as long as... well, I had one once that didn't recover at all, with its outputs (contacts) stuck in an intermediate state. I assume this was due to friction.

Regards, Allan

After measuring Virtex 2 Pro behavior, I calculated the metastability capture window to be less than

0.1 femtoseconds. Pretty small indeeed. Peter Alfke (back from vacation)