I have a continuous stream of 10us square pulses with a period of
50us coming from a signal generator. I'd like to select bursts of N of these pulses to send on to another instrument by combination of the pulse stream with a gate signal in an AND gate. The pulse stream and the gate come from 2 different non-synchronized systems.
The trouble is this: if I make the gate signal N*50us wide I get sometimes N pulses at the output of the AND gate, and sometimes N+1 pulses (a runt at the beginning and the end of the gate, and a full pulse in the middle). If I make the gate N*50-10us wide, I get sometimes N, sometimes N-1 pulses. Is there some way to do this so that I always get N pulses?
Use a - say - 15usec monstable triggered on the leading edge of your
10usec pulse to block the gate signal, and a second - say - 45usec monstable triggered at the same point to create a 30usec wide window where you can turn on your gating signal in the certain knowledge that it isn't going to chop any of your 10usec pulses in half.
You will need to work out worst case tolerances on your monostable output transitions vis-a-vis your 10usec pulse edges, and if the clock controlling your 10usec pulse width and your 50usec pulse period isn't the same clock that controls with width of your gating signal you will have to work out how large you can let N be before the position of the trailing edge of the gating signal becomes uncertain enough to risk getting into one of the 10usec pulses.
If the clock available in the system that generates your gating signal is fast enough, you can use triggered counters to replace the two monostables.
use a D-type falling-edge-triggered flip-flop to synchronise your gate signal __ .----------------------------| \\ | _____ | & |---- out Pulse source -------------+----|clk | .-|__/ | | | gate source -(60us one-shot)----|D Q|---(one shot)--' `-----' adjust for N pulses
That will produce a trailing glitch when the turn-off pulse arrives. It will sneak out the AND gate until the propagation delay of the FF+AND turn it off. Someone else suggested the same arrangement but with the clk input inverted, which makes more sense.
There are many ways to synthesize a gate that lets exactly 50 pulses through, but then it's not the gate you started with. Might as well just use a trigger to generate 50 pulses. And if you're gonna do that, might as well just skip the hardware and assume you got 50 pulses and be done with it...inputcounter = inputcounter + 50
If there's some timing relationship between the two sources that you're trying to preserve, you need to specify what you want.
And we haven't even started thinking about what to do with the race condition when the two edges are coincident...give or take a little.
So, what are you trying to accomplish? 90% of the solution is deciding what the problem is...
Speaking old TTL circuits, a 7400 and a 7474 will do the trick. There is a delay as two flipflops are used. This is done to prevent glitches when the gate timing signal changes during the setup time of the first flipflop.
Another approach is to relax the requirement of using the pulse generator, and just use an astable multivibrator. You hang a counter on the output of the astable, and either reset or jam-load it ('asynchronous preset' in data sheet lingo) when the trigger arrives.
When the counter resets, the astable starts up right away, produces N pulses, and then gets reset by the counter. That stops the counter's clock, of course, so it hangs up there until the next trigger arrives.
You have to worry about a few details: (1) whether the astable's output changes immediately after reset goes away, or half a cycle later; (2) choosing a counter and a reset or jam load scheme (you might have to load 50 or 51 for a down-counter, or 13 or 14 for an up-counter, for instance); (3) making the counter's output do the right thing for the reset pin of the astable; and (4) making sure the first pulse from the astable isn't anomalously long.
The 555's timing capacitor swings from 1/3 to 2/3 of Vdd in astable operation, but when it's been reset, the voltage decays all the way to zero, which makes the first pulse something like half again too long. You can make a bandaid solution for this by connecting two caps to the timing pin: C1 connected between TIMING and ground as usual, and C2=C1/2 connected between TIMING and RESET'. That way, when RESET' goes high, the total RC gets initialized to Vdd/3, so the first pulse is similar in length to the rest. The bad news is that it loads down the RESET line. (It also might pull TIMING below ground if RESET' arrives at the wrong time, but a resistor in series with RESET' will protect against that.)
If the astable's output doesn't change immediately when the reset arrives, you can XOR it with the reset signal from the counter--though you have to watch out for glitches on the last clock if you do that.
To clarify a bit: the system generating the pulse stream (system A) runs at its own, stable, frequency. System B generates a gate which is asynchronous to system A to say: "give me the next N pulses from system A." The only way I have of specifying the number of pulses N is through the width of the gate.
A lot of you suggested using a synchroniser based on a flip-flop and a AND gate. This would seem to work just fine, all I have to do is generate a gate that is N*period wide (N=2 here):
_____|¨|_____|¨|_____|¨|_____|¨|_____|¨|_____|¨| pulses ¨¨¨¨¨|_|¨¨¨¨¨|_|¨¨¨¨¨|_|¨¨¨¨¨|_|¨¨¨¨¨|_|¨¨¨¨¨|_| pulses' A __________|¨¨¨¨¨¨¨¨¨¨¨¨¨¨¨|_____________________ gate _____________|¨¨¨¨¨¨¨¨¨¨¨¨¨¨¨|__________________ sync'd gate B _______________|¨¨¨¨¨|_|¨¨¨¨¨|__________________ A & B
I'm using a falling edge triggered D flip-flop to do the synchronising, and inverting the pulses going into it.
This gives me 2 rising or 2 falling edges in the output to trigger on, which is OK. But what happens, as some have suggested, when the rising edge of the gate happens to coincide with a falling pulse' edge (and its falling edge therefore coincides with another)? It looks like, no matter what i do in this case, I'm back to the problem of having one more, or one less, trigger edge in the output than I want. Or can the addition of delays, as others have suggested, get around this problem somehow?
If you want the async gate signal to select the exact number of pulses to be let through, you'll have to measure the gate width relative to the trigger rate clock, but to better than one clock resolution. Half a clock might be good enough.
What is the general idea behind it (my experience with logic circuits is nil+epsilon, so I can't read a schematic like yours in detail)? It looks like you're using a counter (pre-programmed with N, I suppose?) Does that mean you agree that the problem is insoluble using only the width of the gate to determine the number of pulses in a burst?