# gated pulse stream problem

• posted

I have a continuous stream of 10us square pulses with a period of

50us coming from a signal generator. I'd like to select bursts of N of these pulses to send on to another instrument by combination of the pulse stream with a gate signal in an AND gate. The pulse stream and the gate come from 2 different non-synchronized systems.

The trouble is this: if I make the gate signal N*50us wide I get sometimes N pulses at the output of the AND gate, and sometimes N+1 pulses (a runt at the beginning and the end of the gate, and a full pulse in the middle). If I make the gate N*50-10us wide, I get sometimes N, sometimes N-1 pulses. Is there some way to do this so that I always get N pulses?

thanks! slim

• posted

Pass the sum to a flip flip? this obvious will scale the output by half. also, an Xor gate seems to come to mind on this for some reason.

"

• posted

latching the gating signal with the clock inverted will avoid the runt pulses, but I'm not sure it will be possible to garantee exactly N pulses, with two async generators

-Lasse

• posted

If the gate must be used to count the pulses, probably not. The gate rising edge cound be used to start a hunk of synchronous logic that counts out exactly 50 clean pulses.

John

• posted

Use a - say - 15usec monstable triggered on the leading edge of your

10usec pulse to block the gate signal, and a second - say - 45usec monstable triggered at the same point to create a 30usec wide window where you can turn on your gating signal in the certain knowledge that it isn't going to chop any of your 10usec pulses in half.

You will need to work out worst case tolerances on your monostable output transitions vis-a-vis your 10usec pulse edges, and if the clock controlling your 10usec pulse width and your 50usec pulse period isn't the same clock that controls with width of your gating signal you will have to work out how large you can let N be before the position of the trailing edge of the gating signal becomes uncertain enough to risk getting into one of the 10usec pulses.

If the clock available in the system that generates your gating signal is fast enough, you can use triggered counters to replace the two monostables.

-- Bill Sloman, Nijmegen

• posted

use a D-type falling-edge-triggered flip-flop to synchronise your gate signal __ .----------------------------| \\ | _____ | & |---- out Pulse source -------------+----|clk | .-|__/ | | | gate source -(60us one-shot)----|D Q|---(one shot)--' `-----' adjust for N pulses

• posted

That will produce a trailing glitch when the turn-off pulse arrives. It will sneak out the AND gate until the propagation delay of the FF+AND turn it off. Someone else suggested the same arrangement but with the clk input inverted, which makes more sense.

```--

http://www.ben.com/```
• posted

A resynchronizer? Don Lancaster had one of these in the TTL cookbook.

Cheers! Rich

• posted

the second one-shot monostable should not turn off until after the final pulse. (but before the next pulse)

• posted

On 2008-12-16, Ben Jackson wrote:

the second one-shot monostable should not turn off until after the final pulse. (but before the next pulse)

the first one-shot is optional as long as the gate signal is goes high (and low) for long enough for the flip-flop to switch.

here's a demo (I built the one-shot from real parts)

there's a bunch of labeled nodes with shifted and scaled voltages that make a pretty timing diagram in the scope window.

Version 4 SHEET 1 2020 724 WIRE -336 -160 -400 -160 WIRE 1696 -160 1632 -160 WIRE -400 -112 -400 -160 WIRE -336 -112 -336 -160 WIRE 1632 -112 1632 -160 WIRE 1696 -112 1696 -160 WIRE -288 -32 -336 -32 WIRE 1744 -32 1696 -32 WIRE -544 -16 -608 -16 WIRE -608 32 -608 -16 WIRE -544 32 -544 -16 WIRE -160 48 -336 48 WIRE 1696 48 -160 48 WIRE 1776 48 1696 48 WIRE 1952 48 1840 48 WIRE 2016 48 1952 48 WIRE 1952 64 1952 48 WIRE -336 80 -336 48 WIRE 1184 80 880 80 WIRE 1712 80 1184 80 WIRE 1776 80 1712 80 WIRE 816 96 464 96 WIRE 1184 96 1184 80 WIRE -496 112 -544 112 WIRE 1952 128 1936 128 WIRE 32 144 -256 144 WIRE 224 144 192 144 WIRE 240 144 224 144 WIRE 336 144 304 144 WIRE 1712 144 1712 80 WIRE 544 160 512 160 WIRE 864 160 768 160 WIRE 912 160 864 160 WIRE 960 160 912 160 WIRE 1184 160 1168 160 WIRE 512 176 512 160 WIRE 960 176 960 160 WIRE -160 192 -160 48 WIRE -80 192 -160 192 WIRE 32 192 -16 192 WIRE -544 208 -544 192 WIRE -384 208 -544 208 WIRE -256 208 -256 144 WIRE -256 208 -384 208 WIRE -384 224 -384 208 WIRE 544 224 432 224 WIRE 832 224 768 224 WIRE 1952 224 1952 208 WIRE 1184 256 1184 240 WIRE 464 288 464 96 WIRE 544 288 464 288 WIRE 832 288 832 224 WIRE 832 288 768 288 WIRE 224 320 224 144 WIRE 832 320 832 288 WIRE 864 320 864 240 WIRE 864 320 832 320 WIRE 1952 320 1952 304 WIRE 224 336 224 320 WIRE 432 352 432 224 WIRE 544 352 512 352 WIRE 1184 352 1184 336 WIRE 224 400 208 400 WIRE 336 400 336 144 WIRE 368 400 336 400 WIRE 512 400 512 352 WIRE 912 400 912 160 WIRE 912 400 512 400 WIRE 832 416 832 320 WIRE 608 448 432 448 WIRE 624 448 608 448 WIRE 224 496 224 480 WIRE 336 496 336 480 WIRE 416 496 336 496 WIRE 608 496 608 448 WIRE 608 496 496 496 WIRE 832 496 832 480 WIRE 832 496 608 496 WIRE 832 512 832 496 WIRE 224 592 224 576 FLAG -336 160 0 FLAG -384 304 0 FLAG -400 -32 0 FLAG -288 -32 pulse_clock FLAG -608 112 0 FLAG -496 112 trigger_clock FLAG 224 592 0 FLAG 208 400 flop_out FLAG 512 176 0 FLAG 960 256 0 FLAG 832 512 0 FLAG 1184 352 0 FLAG 1168 160 mono_out FLAG 1952 320 0 FLAG 1936 128 output FLAG 1632 -32 0 FLAG 1744 -32 pulse_clock2 FLAG 352 -192 pulse_clock FLAG 352 -160 pulse_clock2 FLAG 352 -128 trigger_clock FLAG 352 -96 flop_out FLAG 352 -64 mono_out FLAG 352 -32 output SYMBOL voltage -336 64 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 1 0 0 0 .00001 .00006) SYMBOL Digital\\\\and 1808 0 R0 SYMATTR InstName A1 SYMBOL Digital\\\\dflop 112 96 R0 SYMATTR InstName A2 SYMBOL voltage -384 208 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value PULSE(0 1 0 0 0 .000084 .0006141) SYMBOL res -352 -48 R0 SYMATTR InstName R1 SYMATTR Value 12K SYMBOL res -352 -128 R0 SYMATTR InstName R2 SYMATTR Value 1k SYMBOL voltage -400 -128 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value 1 SYMBOL res -560 96 R0 SYMATTR InstName R3 SYMATTR Value 12K SYMBOL res -560 16 R0 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL voltage -608 16 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V4 SYMATTR Value .9v SYMBOL res 240 416 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R5 SYMATTR Value 12K SYMBOL res 240 496 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R6 SYMATTR Value 1k SYMBOL voltage 224 480 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V5 SYMATTR Value .8v SYMBOL Digital\\\\inv -80 128 R0 SYMATTR InstName A3 SYMBOL cap 304 128 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C1 SYMATTR Value 10n SYMBOL Misc\\\\NE555 656 256 R0 SYMATTR InstName U1 SYMBOL voltage 960 160 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V6 SYMATTR Value 5v SYMBOL cap 816 416 R0 SYMATTR InstName C2 SYMATTR Value 40n SYMBOL res 848 144 R0 SYMATTR InstName R7 SYMATTR Value 7.3K SYMBOL npn 368 352 R0 SYMATTR InstName Q1 SYMBOL res 528 336 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R8 SYMATTR Value 1k SYMBOL res 320 384 R0 SYMATTR InstName R10 SYMATTR Value 4K SYMBOL voltage 400 496 R270 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V7 SYMATTR Value .4v SYMBOL Digital\\\\buf 816 32 R0 SYMATTR InstName A4 SYMBOL res 1200 176 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R9 SYMATTR Value 12K SYMBOL res 1200 256 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R11 SYMATTR Value 1k SYMBOL voltage 1184 240 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V8 SYMATTR Value .7v SYMBOL res 1968 144 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R12 SYMATTR Value 12K SYMBOL res 1968 224 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R13 SYMATTR Value 1k SYMBOL voltage 1952 208 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V9 SYMATTR Value .6v SYMBOL res 1680 -48 R0 SYMATTR InstName R14 SYMATTR Value 12K SYMBOL res 1680 -128 R0 SYMATTR InstName R15 SYMATTR Value 1k SYMBOL voltage 1632 -128 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V10 SYMATTR Value .5 TEXT -418 332 Left 0 !.tran .01 TEXT 280 -232 Left 0 ;probe thses nodes to get a timing diagram in the scope

• posted

Try...

Newsgroups: alt.binaries.schematics.electronic Subject: "Burst" Generator - BurstGeneration.pdf Message-ID:

...Jim Thompson

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| James E.Thompson, P.E.                           |    mens     |
• posted

```--
"Gated pulse stream problem" on sed:

news:466jk4l99i6fu2hi0tn29a3qie8v3eu3d3@4ax.com```
• posted

What are you trying to accomplish?

In the general case, it can't be done.

There are many ways to synthesize a gate that lets exactly 50 pulses through, but then it's not the gate you started with. Might as well just use a trigger to generate 50 pulses. And if you're gonna do that, might as well just skip the hardware and assume you got 50 pulses and be done with it...inputcounter = inputcounter + 50

If there's some timing relationship between the two sources that you're trying to preserve, you need to specify what you want.

And we haven't even started thinking about what to do with the race condition when the two edges are coincident...give or take a little.

So, what are you trying to accomplish? 90% of the solution is deciding what the problem is...

• posted

"Slim Gaillard" schreef in bericht news: snipped-for-privacy@mid.individual.net...

In the first place you'd better take a gate timing of N*50+5 or N*50-45. This way, only one of the gate timing edges can interfere with the a clock edge.

From the top of my had, I remember I solved a similar problem with the circuit below.

clock--+--------------------------------------+ | | gate---)-------------+ | | __ | .---. .---. | __ __ +--+--| | +-|D |------|D |----+ +--| | +-| | | |& |o-+---|> | +-|> | | |& |o-+ |& |o--burst +--|__| | | |o- | | |o- +-----|__| +-|__| | '---' | '---' +------------+ created by Andy´s ASCII-Circuit v1.24.140803 Beta

Speaking old TTL circuits, a 7400 and a 7474 will do the trick. There is a delay as two flipflops are used. This is done to prevent glitches when the gate timing signal changes during the setup time of the first flipflop.

petrus bitbyter

• posted

Another approach is to relax the requirement of using the pulse generator, and just use an astable multivibrator. You hang a counter on the output of the astable, and either reset or jam-load it ('asynchronous preset' in data sheet lingo) when the trigger arrives.

When the counter resets, the astable starts up right away, produces N pulses, and then gets reset by the counter. That stops the counter's clock, of course, so it hangs up there until the next trigger arrives.

You have to worry about a few details: (1) whether the astable's output changes immediately after reset goes away, or half a cycle later; (2) choosing a counter and a reset or jam load scheme (you might have to load 50 or 51 for a down-counter, or 13 or 14 for an up-counter, for instance); (3) making the counter's output do the right thing for the reset pin of the astable; and (4) making sure the first pulse from the astable isn't anomalously long.

The 555's timing capacitor swings from 1/3 to 2/3 of Vdd in astable operation, but when it's been reset, the voltage decays all the way to zero, which makes the first pulse something like half again too long. You can make a bandaid solution for this by connecting two caps to the timing pin: C1 connected between TIMING and ground as usual, and C2=C1/2 connected between TIMING and RESET'. That way, when RESET' goes high, the total RC gets initialized to Vdd/3, so the first pulse is similar in length to the rest. The bad news is that it loads down the RESET line. (It also might pull TIMING below ground if RESET' arrives at the wrong time, but a resistor in series with RESET' will protect against that.)

If the astable's output doesn't change immediately when the reset arrives, you can XOR it with the reset signal from the counter--though you have to watch out for glitches on the last clock if you do that.

Cheers,

Phil Hobbs

• posted

To clarify a bit: the system generating the pulse stream (system A) runs at its own, stable, frequency. System B generates a gate which is asynchronous to system A to say: "give me the next N pulses from system A." The only way I have of specifying the number of pulses N is through the width of the gate.

A lot of you suggested using a synchroniser based on a flip-flop and a AND gate. This would seem to work just fine, all I have to do is generate a gate that is N*period wide (N=2 here):

_____|¨|_____|¨|_____|¨|_____|¨|_____|¨|_____|¨| pulses ¨¨¨¨¨|_|¨¨¨¨¨|_|¨¨¨¨¨|_|¨¨¨¨¨|_|¨¨¨¨¨|_|¨¨¨¨¨|_| pulses' A __________|¨¨¨¨¨¨¨¨¨¨¨¨¨¨¨|_____________________ gate _____________|¨¨¨¨¨¨¨¨¨¨¨¨¨¨¨|__________________ sync'd gate B _______________|¨¨¨¨¨|_|¨¨¨¨¨|__________________ A & B

I'm using a falling edge triggered D flip-flop to do the synchronising, and inverting the pulses going into it.

This gives me 2 rising or 2 falling edges in the output to trigger on, which is OK. But what happens, as some have suggested, when the rising edge of the gate happens to coincide with a falling pulse' edge (and its falling edge therefore coincides with another)? It looks like, no matter what i do in this case, I'm back to the problem of having one more, or one less, trigger edge in the output than I want. Or can the addition of delays, as others have suggested, get around this problem somehow?

_______________|¨|_____|¨|

• posted

pulses' A

I think my posted schematic will always give you N pulses. It may just take as much as a CLK period to start the first output pulse.

...Jim Thompson

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| James E.Thompson, P.E.                           |    mens     |
• posted

If you want the async gate signal to select the exact number of pulses to be let through, you'll have to measure the gate width relative to the trigger rate clock, but to better than one clock resolution. Half a clock might be good enough.

Tricky.

John

• posted

```--
I\'ve posted a simple four chip solution for you on
alt.binaries.schematics.electronic which I\'m pretty sure will work.```
• posted

What is the general idea behind it (my experience with logic circuits is nil+epsilon, so I can't read a schematic like yours in detail)? It looks like you're using a counter (pre-programmed with N, I suppose?) Does that mean you agree that the problem is insoluble using only the width of the gate to determine the number of pulses in a burst?

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