FPGA Journal Article

Thank you for the kind words Eric. P.S. has everyone read Eric's article about FPGA Gaming in XCELL?

Last really open system was the XC6200. But it failed commercially, at least in part, because it was a finer grained architecture.

FPGA capacities should now be big enough to support a "virtual FPGA" layer on top of a real FPGA, using only the "public" parts of the bitstream (e.g BRAM and SRL16 contents, possibly a subset of the routing) to give a completely open format. Possibly a virtual XC6200, but probably a coarser grained architecture (mini-Spartan perhaps). I wonder what size Spartan-3 you would need for a virtual XC6264?

This would lose a lot of capacity and performance (you may need several LUTs dedicated to routing for every one you can use for logic) but the result is likely to be at least competitive with the sort of technology a startup or small player has on offer.

I think it would be big enough to exercise open source development tools until something better came along...

- Brian

it has already been done there was MPGA project that implemented a virtual "Meta" FPGA the project is dead vanished/vanishing but its a nice a example of the use of SRL16 for virtual FPGA loading

its however far more interessant to implement dynamic bitstream generator that patches some parts of the ready made bitstream to modify the algorithm this needs to no resources to be vasted for the download of the new config.

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Antti Lukats
http://www.xilant.com

Hmm... will google show me this? :)

All the better to have documentation, no?

I happen to disagree. We are all entitled to our opinions of course. If the vendors would have a well defined format to "compile" to, and a good library/port for a program to be able to take this format and then generate a bitstream, that would be a start. Note, I'd want to have the source available to be so that I could port this last bit of "technology" to my favourite OS (by choice or necessity).

I can't believe that these things are anything but simple portable ANSI C (or some derivative)...

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 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

At that point, why not create an ASIC... (yeah, price, etc, etc)

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 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

Tobias, this subject has been discussed ad nauseam, in this newsgroup and elsewhere. The reason for the "secrecy" is not so much fear of giving away secrets to a competitor, but rather fear of becoming inundated with support issues. We have about 100,000 designers using our parts, a few dozen of them exploring and abusing subtle aspects could easily bring our support hotline (and this newsgroup) to its knees. Also, the non-open nature of the bitstream provides our customers a certain level of security against reverse-engineering rip-off. Our primary obligation is to remain an innovative and profitable company, to the benefit of our customers, our employees, and our shareholders. Satisfying exotic academic research is fine, as long as it does not conflict with the primary obligation. Just my personal opinion... Peter Alfke

I'm also one of those rebirth hobbyists.

I was a hobbyist up until the mid to late 80's. Probably the most ambitious stuff I tried was a 68020 board with dynamic ram, running at

16Mhz, all on a big wire-wrap board. Back then, the board was stuffed with LSTTL chips. The board was none too reliable -- flex it the wrong way, and something broke. But on a good day, it worked.

I tried to make some improvements for reliability. I played with bipolar PALs. Expensive, and I really hated throwing them away when I made a mistake in programming them. I also tried making my own double sided printed circuit boards. Lithographic film, developed in a close bathroom in my apartment. Needless to say, making and drilling these boards was a fiasco.

So I just stored all my parts away for 15 years or so.

What's changed to get me back into this hobby? Three things.

1) Flash programmable microcontrollers, i.e. PICs and AVRs. None of this burning EPROM business anymore. No wiring up SRAM or DRAM. Just program and go.

2) Low cost schematic/PCB design software and PCB boardhouses. I wouldn't even attempt to make my own boards anymore. And I can get 6 and 8 layer boards, something I'd never attempt as a hobbyist. Woohoo! Soldering those SMD components is a bit of a challenge, especially the PQFP208 packages. Of course there are some interesting things in BGA packages, but I haven't reached the level of craziness to try the toaster over reflow method.

3) FPGA's! I last looked at programmable logic in the bipolar PAL days. I happened to be looking through a Digikey catalog one day and noticed stuff from a company called Xilinx. Hmm, checked their website. Hey, this is pretty neat stuff! And since Digikey (and Xilinx to a limited extent, hint, hint) allow small orders, I can actually get parts. In the 80's, I often had to try going though a rep or Big Distributor, and most wouldn't deal with me at all.

So nowdays, I typically design a board with a microcontroller on it, slap a Spartan chip of some sort on it as well, and worry about how to make it work later. Aside from a few early gotchas, like trying to use an input only pin on an FPGA as an output, this has worked very well.

I've weaned myself away from schematics for CPLD/FPGA design and taught myself VHDL. To me at least, it's a very different mindset to think in, but it's getting easier as I do more designs. I still struggle with VHDL which looks legal but isn't quite right for synthesis, trying to interpret some obscure message from WebPack.

Now I'm looking to do even more. I keep checking to see when the Spartan

3E board is available. I've worked with the Spartan 3 eval board from Digilent, so I'm anxious to see what's next.

And then there's the little matter of the ML403 kit Xilinx offers with the Virtex 4 FX and the EDK. As a hobbyist, I'm cringing at the thought of putting $895 into this. At the same time, I'm going, hmm, what could I do with the PowerPC chip or the MicroBlaze? Hmm, no it's too much money.... But I keep thinking about it :-) I know Xilinx doesn't really target people like me, but I keep hoping for a half-price sale or a hobby bundle on the ML403 (no support, no commercial use or you give up your first born, etc).

Cheers,

Scott

snipped-for-privacy@earthlink.net

The problem is the bitstream is very tightly tied to the architecture of the FPGA cell. Having a well defined format tightly constrains the FPGA architecture to the one the bitstream format is published for. What that means is that either the format has to change for every fpga variant out there, now and in the future, or the FPGA has to be frozen in order to comply with the bitstream format.

There is far more coupling between the bitstream in an FPGA and its hardware than there is between an instruction set and a processor architecture because of the fine granularity of the configuration of the FPGA. In other words, an instruction set in a microprocessor controls relatively few connections between some very complex blocks. The FPGA bit stream controls many many connections between lots of small simple blocks, so if the bitstream format is predefined by a standard there is very little lattitude for evolving the FPGA's structure.

I'm not sure I see what the big push for having bitstream access is. I've yet to see a compelling need for it that is not addressed by the existing tools (there is always XDL if you really want to bit bang). The only reason that seems to surface is to allow outside parties to develop their own place and route tools. Frankly, I don't think the complexity of modern FPGAs is such that this type of undertaking can improve on or even compete with the free place and route tools already offered by the FPGA vendors in the timeframe between device introduction and obsolescence. Anyway, for those hadry enough to try, as I said, the XDL tools do give you enough access to every step of the design flow to allow you to play with any step you feel compelled to play with.

Hobbyists. Now there's a term you don't often hear amongst the next generation. If the hobbyist is going to make a comeback in this country (US) it is going to take more than a low-cost, high capability FPGA. With the watered down public education serving up a non-challenging, push them through curriculum, what hope is there for technologists in this country over the next few decades?

Do you know how many times I've walked into a gas station and encountered a teen who can't carry through on a simple transaction? The youth today aren't--for the most part--go getters: they lack direction, motivation, and personal responsibilty. They are not problem-solvers, they're problem-makers who go though life thinking that somebody is always going to wipe their backside. Give them a kit of parts and ask them to make it work-ha! They might have to read a book!

It has been reported that high school graduates are increasingly choosing non-technical fields to major in. The technical fields are too challenging, require too much work, and interfere with the 50hrs/week of playing video games. Where are the Heathkitter's of the next generation?

I've ranted long enough...........................

Peter:

I appreciate your comments. But do you know how many great civilizations have come and gone since Socrates, including his [Socrates] own? I'm an old patriot and my response was mainly driven by my frustration of what I see as a possible future for this great country. I work for a fortune 500 company and I don't see many young Americans coming in for internships. I have also worked with one of our local well-renonowed colleges and I see a majority of students with visas filling the class rooms, not young Americans. Yes, there are many great engineers in this country ,and doubtless there will be many more, but I fear that those numbers will fall.

And don't mis-interpret my message: I'm not against anyone coming to this country to get an education. To re-state, I'm just frustrated with our primary education system.

My apologies for deviating from the topic--it just hit a nerve.

Take care, Rob

I've had some interesting conversations with Tutors, and one point they make for the lack of inflows, is the 'appliance' nature of much of the electronics. No one enters tertiary education expecting to design a stereo, or TV, plus much of what potential students see is disposable, or close to disposable. Then the Dot-bomb tended to tar all technology companies with the same brush, and the industry is still clawing back from that.

That's why I believe such 'early/wide student' demos, need to have at least one block that has a wide audience. ie something they can show their parents, or apply to a club, or sport.

GPS-option Stopwatch is one such item : Give them time displays to the low ns, just to remind potential students of the reach of the time-domain. - and make it simple enough for even schools to run as 'canned examples'.

-jg

Peter Alfke wrote:

Tobias Weingartner schrieb:

JBits is a solution to all this. Maybe not a particulary good one, but you can read, modify, write bitstreams in a platform independant way. There is no source code available, but java bytecode that you can essentially call by any language you want on any platform you want.

There are even people at xilinx working on a virtual file system to mount and modify the configuration of a virtex-4 by the embedded PowerPC.

Kolja Sulimma

Scott, I'm genuinely surprised. In my experience, wire-wrap boards were the most reliable boards I've ever had. Especially if you took the time to train the technician how to wire-wrap properly. The hardest point was trying to stop them grouping the wires together into "crosstalk-of-death" busses instead of just connecting them point-to-point. Second hardest was banging into their heads to connect multi-drop traces every other section first, so you can rip up and re-route easier later on. Happy days! Cheers, Syms.

Getting data from the analyzer hardware to the host computer isn't a problem. It's cooking up a nice display on said host computer that's the problem, at least for me. I plead "Hardware guy, your Honor."

I will say that it was easier to get my HID stuff working on Mac OS X than it was on Windows.

-a

NDA's don't count as open. Is the Atmel part 'capable'?

Where can one find more info on NCD and XDL file formats (and what the acronymns stand for)? Are you implying that if one has this NCD file that one can figure out the bitstream format?

Phil

Sure it might change with each new FPGA (or it might even change more often than that). Still the information is somewhere. Right now I'm sure there are internal docs at Xilinx/Altera which document the formats for their tool developers. What would be so bad if they also put those on the web (with a caveat of course that says, "you're on your own: we don't support you playing with the bitstream directly, but if you want to have at it")

I guess I'll have to look into this XDL to see what it is. Is it a higher level description of the bitsteam format?

You're probably right, but people want to be able to tinker. There's the push for open source tools as well as academic research into P&R algorithms, etc. People have lots of reasons for wanting to try these sorts of things.

I'll have to google for XDL.

Phil

It looks like JBits is a University-developed tool. why wouldn't the source code be available?

interesting.

Phil

Interesting idea. Are you saying that a XC6200 model would be developed in HDL and then run through synt, p&r, etc. and that could then be used for downloading the bitstream to?

...but like you say, you would be taking a big performance/area hit.

If you were going to do that, then why not just create some sort of higher level Virtual FGPA device (kind of like what a Virtual Machine is to the software world) that would have lots of nice high-level features (high-level macros available, etc.) and also be tunable for the underlying architecture (depending on whether the target was Xilinx, Altera, or Lattice. Just as VMs allow for easier porting, greater genericity, etc. maybe something like a VFPGA could have similar advantages? Also, just like the Java VM doesn't care what underlying architecture it's running on, this sort of thing could potentially make it easier to port designs between FPGA families... I wonder if it could be done such that there is a minimal impact on performance and area?

Phil