I am looking for data showing typical development times for FPGA based designs. I am trying to compare the cost of implementing a complicated DSP system with different signal processing architectures. I have a good idea of how long the development time would be for a progammable DSP and for an ASIC, but I don't have a feeling for how long the development time would be with an FPGA based solution. I have tried the cost calculator from Xilinx, but I have to say I am quite skeptical in regards to the cost estimate. Why would the development cost for an FPGA system be so much cheaper than an ASIC solution? An ASIC solution at 90nm is generally quoted as $20-30M, but an FPGA solution is supposedly "almost free". The only difference I see between the two are in certain aspects of the back end flow, mask costs, packaging design, and production costs. The up fron design and verification work would be the same for both platforms I assume. What am I missing?


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"crazyd" wrote in news:1107964781.979024.297810

This is a question that is virtually impossible to answer out of context. We are releasing a couple of boards that combine a SHARC DSP and Cyclone FPGA. I think it is much easier to use the DSP for DSP and general purpose control, but that rolling certain go fast algorithms into the FPGA would not take very much time.

Al Clark
Danville Signal Processing, Inc.
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Al Clark

Aye, well they are going to be trying to sell you an FPGA solution ;-)

The verification of an FPGA design can be done incrementally as it grows. I have read of several ASIC developments that have used FPGAsolutions to allow (lower performance) system testing before committing the ASIC to production.

You can also add test/verification functionality to FPGA desings to test various aspects of your design, and thorough system tests can be carried out much more quickly than things can be simulated.

The up front engineer hour cost of the design development will probably be roughly the same for the two development approaches though.


------------------------------------------------------------- Nial Stewart Developments Ltd FPGA and High Speed Digital Design

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Nial Stewart

for DSP I would agree that the main difference is going to be in the back-end physical design flow and the associated NRE costs. There is no difference in terms of methodology or cost for the front-end design work: HDL coding, verification, regression test development etc.

Modern FPGAs have complexity rivalling ASICs of just a few years ago and consequently require the same discipline in design methodology. All that being said I do think there is roughly an order of magnitude cost difference in developing an ASIC vs. FPGA. The physical design portion of ASIC development is a very complex undertaking and mask costs are exploding. And if you have a serious bug in the ASIC, that doesn't have some kind of software work-around, you can spend several 100 k for more mask changes to implement the ECO and an associated schedule hit of months. Because of the consequent paranoia of ASIC bugs and their associated expense, teams tend to take more time in the verification effort. So your development time is quite a bit longer than with an FPGA where a bug is not so tragic.

With an FPGA, if you missed something in verification and that bug shows up in the system bring-up, your only costs to fix it will be the debug time and redesign time. Plus, you can make much more extensive fixes, even feature upgrades, provided they fit into your chosen device. You're not limited to changes constrained by what can be implemented through metal mask changes as in ASICs. The flexibility of the FPGA is a big bonus if the device can meet your speed, power and cost targets.

One last thing: in DSP applications it is often true that you need to prototype the system and fine tune the algorithms because modelling may not cover everything. One example is the design of radio channel modems. Its tough to completely model the channel and be sure your algorithms work under all conditions. With an FPGA implementation significant changes to the algorithm are still possible during field trials on the platform that will actually ship. This may not be true for an ASIC implementation (depending on the degree of its configurability and programmability).


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