FPGA as host for a USB peripheral

It's doable in hardware, but extremely complex. The enumeration process needs quite a bit of decisions making.

However, once the enumeration is complete, there is no reason why other endpoints (non-zero) could not be 100% hardware interface pipes.

Not sure what your interpretation of "high bandwidth" is, but USB 2.0 only goes to 480 Mbits/sec, or about 60Mbyes/sec. So it should be quite trivial to do this in FPGA. However you will need a High Speed USB PHY.

Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

Rudi,

Is it possible to "cheat" and reduce this complexity, if I know that I will literally only ever have exactly zero one specific device connected?

Are there any free/commercial IP cores around that could help with this?

It doesn't matter if it can be done completely in hardware. The only reason I wanted to mention high-bandwidth was for the case where I would have to use a soft-core processor as the complexity of driving the USB host controller is too great to be feasible in anything but software. Then of course I would have the consideration that the processor would need to be fast enough to handle passing through the data.

Thanks for the suggestions,

- Jake

Jake,

Yes, thats definitely possible. You could skip a lot of the steps if you know the device that will be attached.

We only have commercial host controller IP Cores. Check our web site for more info.

Well, the control path and data path can be separate. You can have a small low end MCU doing the enumeration, and a pure hardware based data pipe for the endpoints. It all depends on how robust you rimplementation has to be ...

Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

need

Is there a special USB slave device that enumerates and configures hosts?

"Jacob Bower" skrev i meddelandet news: snipped-for-privacy@sprite.doc.ic.ac.uk...

kind

Question is if you can do it cost effectively in an FPGA. If you take an intelligent USB Host like the AT43USB380, you still need an external micro with about 64 kB of memory just for a single driver (for Mass Storage). Maybe your device class is simpler but uyou probably need a soft MCU and around 16 kB of code just to run the USB Host Stack without any device class.

If it is point to point, why need USB at all?