Open-Source MicroBlaze IP-Core working in FPGA :)

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here is proof :)

the opensource version as available from opencores is not yet good enough to run uCLinux - well lets see if that will change, I think there is a wish to have an open-souce multi-vendor FPGA softcare capable to run uCLinux inside many people :)

Antti

Reply to
Antti Lukats
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And this is what irks me...if you "need" a "free" FPGA cpu core, there are already several to choose from

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One of them even has a full GNU-tool chain. So what makes the Microblaze so special? Is it because it has some industry recognition, better performance/functionality, or is it simply because more people have already used it, and want to continue use what they're familiar with?

Maybe it's because Xilinx poured in a lot of R&D into Microblaze, proved the design, and are committed to future support of it. Enough customers haved used the design that people in the industry collectively 'know' its strengths/weaknesses.

Sorry I went off on a rant...I'm struggling to understand why OpenRISC 1k, despite being 'proven' for more than a year, isn't really showing up anywhere.

For ASICS, the answer is obvious -- just the mask-order (for 0.18u standard cell) is $300,000USD -- big enough that no sane engineer will 'sign-off' on a free design with no proven track record. For FPGAs, well there's the Xilinx Microblaze at $500 USD (and the Altera Nios for similar cost) -- an insignificant fraction of a US engineer's salary.

I suppose the upside is that old engineering saying: "copying is the highest form of flattery." :)

Reply to
whatisasics

I could be wrong, but I thought open source cores that run uCLinux were already available for FPGAs. The only difference is that this one is code compatible with uBlaze. Am I wrong about this?

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Rick "rickman" Collins

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Reply to
rickman

what is the use/future of dsprocessors in vls

-- thevlsiguruwww.totallychips.com - VHDL, Verilog & General Hardware Design discussion Foru

Reply to
thevlsiguru

LEON is an implementation that is focused on a radiaton hard operation of an architecture (SPARC) that was designed for ASICs. Whereas MB is an architecture that was optimized from the beginning for a small FPGA implementation. There will never be a SPARC implementation that will get the same performance per LUT as MB does. AFAIK the OR1k architecture also is not optimzed for FPGA implementation and is therefore rather large.

So I think it is great to see an open source implementation of MB. Can you comment on how many LUTs your implementation requires? Also: You mention on your web site that some instructions are not impleneted. Which instruection are these?

Kolja Sulimma

Reply to
Kolja Sulimma

It is designed for radiation hard per se? Isn't it just an open source SPARC. Do you knwo how to design for radiation hard applications, especially in an FPGA? Redundant structures and hoping that the synthesizer does not detect them and optimize it away...

Martin

Reply to
Martin Schoeberl

enough to

I dont know what the "irks" means, but - if it really irks you then please please:

1) goto to opencores, 2) download any of the several cores you mentioned 3) port the uCLinux reference desing for that core to the FPGA board you use 4) boot uCLinux to the shell prompt on your FPGA board

I would really like to hear your comments after you have managed 1..4 from above! And please post with your real name not using anon email address!

Antti PS porting MicroBlaze-uCLinux reference design (mbvanilla) to new FPGA board takes usually less than 5 hours

Reply to
Antti Lukats

enough to

Hi Rick,

Yes, OR1K is uCLinux capable, I guess also M68K and LEON and maybe Aquarius/SH-3 could be.

The thing is that MicroBlaze-uCLinux reference design (mbvanilla) requires

1) any FPGA starting from XC2S200 2) 4MB SRAM/SDRAM/DDR 3) interrupt/timer/uart 4) porting of the mbvanilla to new board can be done withing few hours

ASFAIK there is nothing to compete with that - OR1K reference design doesnt pass even synthesis out of box, just tried out of curiosity.

MicroBlaze is small and minimal MicroBlaze-uCLinux is small as well, actually there is almost no overhead to make MicroBlaze system uCLinux reference design compatible.

Yes, if there would be similar reference platform for OR1100, but it is not available. LEON is real nice system, but the ref system hardly fits into XCV2000 !! M68K is not complete i think and SH3, not sure if there is uCLinux available for it all.

So you are not wrong per se, but I dont envy you if you try to use some existing open ip core for the uCLinux bringup.

antti

Reply to
Antti Lukats

What happened to all this implementations of the DLX ? There was the whole GNU chain available at one time, and a lot of people used them for their diploma work etc...

Reply to
E.S.

donate my

Hi Antti,

that's really nice (and funny) how much used this single board gets ;-) And a MB on an Altera FPGA, that's the end of the world. BTW: I have some more ACEX boards. I could donate them (or a small fee..) for projects that can convince me...

Martin

Reply to
Martin Schoeberl

were

not

First: its not my implementation at all, I am just trying to find some funding for the original author, actually openchip is already sponsoring the project a little

Device utilization summary:

--------------------------- Selected Device : 2v1000fg256-5 Number of Slices: 614 out of 5120 11% Number of Slice Flip Flops: 347 out of 10240 3% Number of 4 input LUTs: 972 out of 10240 9% Number of bonded IOBs: 34 out of 172 19% Number of BRAMs: 4 out of 40 10% Number of GCLKs: 1 out of 16 6%

Timing Summary:

--------------- Speed Grade: -5 Minimum period: 8.573ns (Maximum Frequency: 116.645MHz)

The above includes 256 words distributed ROM CPU itself is even smaller.

The current release does not have any optional instructions what as such is not a problem. There is also no interrupt implemented yet, so that is biggest issue at the moment for the uCLinux at least, but I have done pretty many useful Microblaze design without using interrupts so its not useless at all.

I just did make a example test implementation similar to xilinx ultracontroller, ie bram on dataside and bram other side to gpio and I would say that open source MB could be very nice ultracontroller-lite already at this stage of development! And being so tiny and being supported with GNU toolchain its a nice beastie !

Ha, I see Martin has also already responded, for I just offered to donate my acex jopcore PCB to the MB designer, so it goes for good cause at last!

And for others too, if somebody has some FPGA development board, the open-source microblaze author does not have *any* FPGA hardware to test with at all, all the work is done with plain testbenching using free verilog simulator - so if there is some overleft FPGA board (preferable suitable for uCLinux i.e. with rs232 and at least 4MB RAM) please consider donating it for the open-MB/uCLinux project.

I am not asking it for myself, I have most of the boards I want (except that I am looking for MAX2 devboard) - unfortunatly i dont have so much suitable boards for donation myself (what I have overleft I have already promised to give away to the project)

Antti

RE: LEON/Sparc and OR1K, yes both are HUGE !! OR1K with only UART and all stuff stripped out is 77% of V2-1000 I dont have stripped out LEON synth but its possible even larger. same for nnARM its huge as well :(

so as for the moment the open-MB is the smallest free-open IP-core with "proven" gnu toolchain support I would say, or does some better alternative exist ??

Reply to
Antti Lukats

I am looking at prototyping boards for a CPU in an ACEX 1K50. Do you have anything with that chip? How much would you want for it?

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Rick "rickman" Collins

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Reply to
rickman

If the project needs a board, what exactly do they need? I belive there is a Spartan 3 dev board for $100. I would be willing to spring for one of those if that would do the job.

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Rick "rickman" Collins

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Reply to
rickman

;-)

fee..)

Yes, the boards are with the ACEX 1K50. Is EUR 75,- ok?

Martin

Reply to
Martin Schoeberl

"Martin Schoeberl" skrev i meddelandet news:KvC7d.330190$ snipped-for-privacy@news.chello.at...

The Leon project was funded by the European Space Agency, and the goal was to produce a radiation hardened processor for their Satellites controllers. The rad hardening does not have any effect on the VHDL code AFAIK

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Ulf at atmel dot com
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Reply to
Ulf Samuelsson

(OpenCores Microblaze Implementation)

So the Open Cores implementation is even smaller than the original and not much slower? Good work.

Kolja

Reply to
Kolja Sulimma

Yes and no ;-) The standard version is just an open source SPARC, but it was designed by ESA with radiation hard ASIC implementations in mind. Therefor it is not optimized for FPGA area and not even for ASIC area but for reliability. Also, there is a version with redundancy available.

Either faith as you suggested or keep attributes. Also, you do not need to replicate the whole datapath but you can use error detection codes to reduce the logic overhead. At least for some functions the logic to calculate (in the simplest case) the parity of the result is much smaller than computing the result and then the parity of it.

Kolja Sulimma

Reply to
Kolja Sulimma

The price sounds good. Where can I get some info on these boards?

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Rick "rickman" Collins

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Reply to
rickman

I think the reasons our mb-uclinux project is a success, with high visibility and good commercial and academic penetration, are its openness, its community, and its independence.

uClinux on Altera NIOS 1 seems to have gone almost no-where, I think partially because the rights to sell the development kit were bundled into Microtronix. The uClinux mailing list now sees a few individuals trying to scrape together the bits and pieces from that project, to get a free, public distribution.

Evidence that Altera learned their lesson comes from the fact that uClinux support for NIOS 2 was announced the same day as the NIOS2 core was available, and AFAIK this time it is free. Good move.

There is/was a port for uClinux 2.0 kernel for OR1K - however I think system performance in generic FPGA fabric might have been an issue. Also, there is more to building a system than justing having a processor and a compiler, you need tools to interconnect system componebts and so on - the Xilinx EDK and Altera equivalent. Without the tools, free or not there hurdle is too high.

Indeed - has anyone reverse engineered NIOS yet? ;-)

Regards,

John

Reply to
John Williams

gets

small

you

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Martin

Reply to
Martin Schoeberl

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