Bowden's BCD clock circuit

What you call Q0 (and my data sheet calls Q1) is the 1 bit of the count. So pins 6,5,3,2 are the count bits representing 4,8,16 and 32. The counter is fed with AC upstream of the rectifier.

The one I posted a link to, has all Q values 1 higher than this lovely picture.

I've decided to build a BCD clock and after searching for a circuit I've decided on Bill Bowden's circuit.

After examining the circuit, though, I'm curious about the circuit giving a pulse every second. There are two NAND gates attached to the

I'm fairly weak on logic circuits so forgive the stupid question.

Greg

View in fixed width font.

Pin 6, 5, 3, 2 are 8+16+32+64 which equals 120 as the divisor so you'll get 1 pulse per second due to the full wave rectifier at the power supply.

Check those Q weights again John....

Yes. That is why I complimented its beauty.

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Right. So the only way the output can go low is if both inputs are low.

The 4+8 gate outputs a low during the counts of 12 through

Then at a count of 28, the 4 and 8 bit are both high, to add to the 16 bit, so the 12 decide goes low again till the count reaches 32, when all the lower bits reset, to be replaced by the 32 bit.

The 12 decide goes low a third time when the total count reaches 32 + 12 = 44, and stays low for 3 more counts through 47. At count 48, the 16 and 32 bits carry the total, and all lower bits are reset.

The 12 decoder goes low a 4th time when the count reaches

The other NAND gate is a 48 decode (16 + 32) that goes low from a count of 48 through 48 + 15 = 63, but of course the count never reaches 63.

Now THAT I didn't notice. Does your data sheet top out at Q12?

The lovely picture is because we're in an non-binaries group. Did you view with Courier?

That is strange that they didn't begin with Q0 as is the norm. can you post the link again?

John Popelish wrote: ...

I forgot the punch line:

So at a count of 60, both NAND gates go low for the first time.

I don't think I explained my question properly. I understand that both of the NAND gates are outputting high normally and either gate will only go low when both inputs are high. So once 32+16 goes high one of the NAND gates will go low and when 4+8 goes high the other NAND output will go low.

My specific question refers to feeding both of these outputs into the OR gate. My understanding is that if either one input OR the other is high the output of the OR gate will be high. So, the OR gate will pulse when 4+8 goes high or 32+16 goes high. (On thinking about the specific circuit now, though, when 4+8 goes high it will reset the counter so that it will only count 12). I think I'm starting to confuse myself, sorry if it sounds unclear.

Greg

I've seen them denoted both ways. An obvious example is Don Lancaster's "CMOS Cookbook", where pin 9 is labelled "1". Indeed, I've used that book so often that it's the one place I can immediately think of, so maybe it's the exception rather than one of a number of places that use the form.

It can be confusing, because if you expect one, then it throws you off when you come across the other.

Michael

Okay, I realise, now, the flaw in my logic. I had forgotten that the OR gate is staying high until both NAND gates went low. I'd also forgotten that the Schmitt trigger / inverter was taking the low pulse from the OR gate and giving the one second pulse. Or, IOW, I got my highs and lows confused.

Thanks for the patience. Now that I see how where I got confused, I feel like an idjit.

Greg

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That's a well written book. I've read all of Don's books in the early years (thanks Don!)

As I recall NOW, the ripple counter simply omitted the first output in order to make pins available. I fell for the "trap".

No need - this is s.e.basics. :-)

Check out DeMorgan's Theorem:

Cheers! Rich