Questioning CD4017 Outputs

That would be correct. RST is an asynchronous reset.

Therefore as soon as a '1' is seen on Q3 the counter is reset so that only Q0 is '1'. On each clock edge the high will advance down the Qs. There will be no more than a "glitch" on Q3 whilst the device is being reset.

Quite rightly Q5 to Q9 should stay low.

Hi Ken

Counters come in many different flavours:

Ring counters - A 4017 is a Johnson counters:

74HC4017; 74HCT4017 datasheet:

Glenn

Is there a way to cause all Q pins to output their respective divide downs at once?

IOW I would like to have divide by 4, 5, 6 and 9 all available at the same time.

Ken Knowles

Four counters works. You can do a /4 followed by /2 to get /6, but /5 and /9 will take individual counters. You're talking about dividing, so you'll have to have a separate counter for each prime factor. It gets even stickier if you want a 5% duty cycle.

The CD4017 is a Johnston counter i.e. a shift register with the final Q and Q- output inverted before feeding into the input again. Each of the ten states are decoded by a two input AND gate between two flip-flops.

Since you are doing an asynchronous reset (RST) before the signal propagates through this shift registers, the high number AND gates never get he correct input combinations and they never produce an output.

The 4017 is a divide by 10 Johnson counter + decoder. If you connect Q3 to the reset you will force it to divide by 3 and will get the following output:

Q2 Q1 Q0

Which is a divide by 3, just as shown in the diagram Figure 1 that you linked to. where Q0..Q2 are Phase1..Phase 3. The difference between the outputs is the phase, the pulse width and frequencies are the same.

Best regards, Spehro Pefhany

That's not what the 4017 does. Without the reset pulse, it outputs high on Q0, then high on Q1, then high on Q2, on through Q9, then back to high on Q0.

Same old pattern: people are trying to be objective and helpful, and JF turns it mean and whiny.

I don't know of any device that operates this way out of the box. It would be a simple matter to program up whatever divides you want in a PLD. There are fairly small devices which can do what you want, but I expect the lack of DIP packages will be an issue for you, no? Perhaps an FPGA eval board will give you what you want? Check out any of a number of low cost eval boards.

So why are you here trying to create drama?

Larkin must be off his meds again. For a week or so there he was quite civil... now he's back to his standard mean-spirited nature. ...Jim Thompson

You might notice that JF, as usual, injected personal nastiness into a collegial technical discussion. He's the one who's in a foul mood. I don't think it's inappropriate to note when people do that chronically.

He has started the usual flame cascade.

And I take all my meds every morning, or almost every morning. They all work pretty well.

I'm stuck in a smallish cabin in the mountains with eight speech pathologists. Guess what: they talk constantly!

As far as the OP goes, I can't understand what he's trying to do, so I have had nothing to say about counters.

So there. Pbbbbttttt!

Actually he didn't. All he did was ask a question. It may not have been overly polite, but it was a far cry from calling anyone "mean and whiny".

Your post was inappropriate by making a personal insult when there was nothing personal previously.

He did pretty much nothing. The "cascade" can only happen if you participate. Why can't you stop participating? Are you compulsive about this? That is a serious question, not intended to be an insult.

So much for your usual defense of "I'm here to talk about technical stuff".

I'd like the group to be polite and technical and professional. JFs post, like most of his posts, was none of the above. He often turns technical posts into flame threads.

You could have said it a little more delicately, we're an emotional breed! :-)