Dual Port RAM

Oct 30, 2006 66 Replies

Andy,

If you like to use the BRAM, it may be loaded with whatever you please by using a software tool to take a hex file, and place it into the bitstream (effectively makes the RAM a ROM).

Since the BRAM is loaded from the bitstream, the default, or initial condition is all zeroes.

This is also true of LUTRAM (it is all 0's to start with, because that is what is in the bitstream).

There is a way to specify LUT contents for the bitstream, but I don't have that handy (net connection at home is slow to download 6 Mb user guides!).

Austin

But then you can't just 'reset' your design. You have to reconfigure from the bitstream to truly reset.

Ben Jackson AD7GD http://www.ben.com/

I agree with you.

I am trying to design a register file as an exercise in design. I have 3 different concepts. Two of the concepts are using traditional registers and the third is using a dual port ram.

They all have to work as register files and have a reset operation which is consistent with each other and the original design. If I cannot reset the register file when using a dual port ram then I've done the wrong thing.

Andy

Yes. But the solution I offered - one "I have been written" register bit per RAM location - doesn't scale well; it's fine for up to a few dozen locations, no more.

If you can arrange that the RAM locations whose initial value matters to you are all in a small piece of address space, you can easily modify the "I have been written" trick so that it applies only to the small part of the memory that has the initialisation requirement.

More generally, it is not unreasonable to consider modifying your system's control state machine so that its first action after reset is to scribble the initialisation values into RAM, maybe by block-copy out of another memory configured as ROM with the reset values in it.

As Peter said, it's not practical to reset a big memory, and people have lived with this for ever.

Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.

Err I only have 3 registers that I must have a reset state for. This should fit well with what you have described. I am trying to code that up at the moment.

The point of this exercise is to get a cycle accurate operation for a register version and a dual port ram version. After that I will look at gate count and or speed.

The issues that I had with not being able to create small dual port rams was selft inflicted. I put the source code into the library when I didn't intend to. OOps.

-- Andy

J>

I just wanted the OP to realize the significant tradeoff he's making by using preloaded blockrams. If you 'reset' a design that uses them you'll be surprised if you expected the reset values to appear in the RAM again!

For something like a processor, I might just require a certain instruction sequence at initialization that sets up the RAMs the way I want. You'd be in good company -- good luck executing anything on a modern Intel processor without following 100 steps in a thick databook...

Ben Jackson AD7GD http://www.ben.com/

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