Hi,
In this thread:
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Peter A. suggested that a Xilinx Virtex2Pro MGT can be used as a high speed sampler.
This requires disabling the CDR in the MGT, so that the receive clock is controlled solely by the reference frequency.
UG024 says: "A... feature of CDR is its ability to accept an external precision clock, REFCLK, which ... acts to clock incoming data..."
I can't work out how to get it to do that, so that it doesn't start using the CDR when the input data has transitions. Presumably there's an undocumented attribute that can turn the CDR off, but I didn't see one in FPGA editor. Any ideas?
BTW, I don't actually want to build something using this right now.
Regards, Allan.