Hi, I am using the Xilinx MGT as PCI-Express specification (Endpoint). As specified in the MGT user manual, we use the Epson's crytstal as the reference clock (125MHz) needs by MGT. But when the add-in card plugs to mother-board, the MGT seems can not lock to the signals from PC. The RXLOSSOFSYNC jumps back and forth between accquired (2'b00) and non-sync (non-zero) state. Can anybody advise me how to debug this. Any comments is appreciate. Thanks.
Jason
Hi,
It likely doesn't lock onto the data stream due to the MGT CDR range and the tolerances of the clocks in the system.
The 125 MHz oscillator you have is probably +/- 100 ppm.
It is likely that the motherboard is providing a 100 MHz reference clock +/- 300 ppm, possibly spread spectrum. It is this same refclk that is used by the root complex. This is allowed by the PCI Express specification. The end result is you could get a 400 ppm difference, which is out of range of the V2Pro / V2Pro-X MGT CDR to reliably lock. This is related to a similar topic that Antti Lukats corrected me on some months ago regarding SATA...
However, if you could use what is called the "common clock configuration" you can reliably lock. To do this you leave off the 125 MHz oscillator and use a clock conversion chip to convert the 100 MHz reference clock from the connector to 125 MHz for the MGT.
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