Filter Output Quantization in Digital Down Converter

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   I am using DDC from Xilinx CoreGen. My application requires a 6MHz
sampled signal (freq = 2MHz, BW = 2MHz) to be down converted to
baseband,resampled at 2 MHZ (ultimately the signal will be at baseband
with 2 sided bandwidth of 2MHz).
   My input bit width is 4. I have configured my DDS mixer to 8 bit
output with SFDR of 25dB. I am not using CIC filter since
downconversion ratio is small (by 3) and also cutoff fc is high (1/2)
w.r.t. lower sampling rate of 2MHz.
   I am using CFIR filter as my decimation filter in each of the I and
Q arm for restricting the signal BW to 1MHz. I am using 15 tap filter
with normalized 8 bit filter coefficients.
   When I generate the core, what I see is, the required output bit
width is 18.
   What I want is my output bit width of the DDC should be 4 bits
(with less degradation in performance of the filter). That means I
have to quantize the filter output. If I quantize uniformly(4 MSBs), I
am obtaining wrong results.
   My question is this. Is it possible to quantize such an output to 4
bits? If not, How can I calculate & justify the number of quantization
bits required at the output?
Any specific references?


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