We're trying to debug a new board with failing DDR3. It's a Xilinx Zynq chip with an ARM Cortex A9 dual core, and built in DDR interface/controller/phy.
We've scoped up the differential DQS lines and are using JTAG to perform reads and writes but there's a lot of unexplained traffic on the line.
Every 7.8us (i.e. tREFI for the DDR) we see a burst of 33 pulses on the DQS (i.e. 64 zero crossings). Between these long pulse trains, there are 39 shorter 5-pulse sets (i.e. 8 zero crossings).
On the (functioning) reference design we based out layout on these DQS lines are silence
Any ideas what the source of this corrupting signal might be?
Thanks, Gareth Owen