using signal as clk source

BUFGP is IBUFG + BUFG, and IBUFG can only be used by signal from GCLK pins.

just use BUFG only. "Tobias Möglich" ??????: snipped-for-privacy@gmx.net...

I use the Spartan-IIE from Xilinx BUFG ist not available for this device. What can I use instead?

And how do I have to implement it in the ucf-file or in the source file (vhd-file)?

Tobias.

The BUFG primitive is available for Spartan-IIE. Which tool or documentation indicates that it not available? Depending on which synthesis tool you use, BUFG may be automatically instantiated in your design.

If you want to directly instantiate a BUFG primitive, here the template provided by the "Language Templates" option inside the ISE 6.1i Project Navigator. To open the templates, start Project Navigator and click Edit --> Language Templates.

Expand the "VHDL" item in the selection tree, then "Component Instantiation", the "Global Clock Buffer", then "BUFG".

Note: You can also invoke Language templates by clicking the "light bulb" icon in the upper right menu bar.

Here is the Language Templates template for the global clock buffer. ____________________________________

-Instantiating BUFGP on Input Port

-- INPUT_PORT: in std_logic;

--**Insert the following between the

-- 'architecture' and 'begin' keywords**

component BUFGP port (I: in std_logic; O: out std_logic); end component;

--**Insert the following after the 'begin' keyword**

signal CLK_SIG: std_logic; U1: BUFGP port map (I => INPUT_PORT, O => CLK_SIG);

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

--------------------------------- Spartan-3: Make it Your ASIC

Here is what I learned from our applications group:

The BUFG primitive is available for Spartan-IIE. Which tool or documentation indicates that it not available? Depending on which synthesis tool you use, BUFG may be automatically instantiated in your design.

If you want to directly instantiate a BUFG primitive, here the template provided by the "Language Templates" option inside the ISE 6.1i Project Navigator. To open the templates, start Project Navigator and click Edit --> Language Templates.

Expand the "VHDL" item in the selection tree, then "Component Instantiation", the "Global Clock Buffer", then "BUFG".

Note: You can also invoke Language templates by clicking the "light bulb" icon in the upper right menu bar.

Here is the Language Templates template for the global clock buffer. ____________________________________

-Instantiating BUFGP on Input Port

-- INPUT_PORT: in std_logic;

--**Insert the following between the

-- 'architecture' and 'begin' keywords**

component BUFGP port (I: in std_logic; O: out std_logic); end component;

--**Insert the following after the 'begin' keyword**

signal CLK_SIG: std_logic; U1: BUFGP port map (I => >