Something simular to the following code fragments works in pre-synthesis simulation, but not in real hardware and post P&R timing simulation.
entity controller is port ( ... datain in : std_logic_vector(7 downto 0); clock in : std_logic; ... lastval out : std_logic_vector(7 downto 0); ); end entity controller;
architecture rtl of controller is begin process(clock) ... variable lastval_v : std_logic_vector(7 downto 0); begin if rising_edge(clock) then case control_state_v is
...
when STATE_CHECK =>
if datain /= lastval_v then lastval_v := datain; control_state_v := STATE_CHANGED else control_state_v := STATE_OTHER; end if;
when STATE_CHANGED =>
...
when STATE_OTHER =>
...
end case; end if;
lastval if datain /= lastval_v then control_state_v := STATE_UPDATE else control_state_v := STATE_OTHER; end if;
when STATE_UPDATE =>
lastval_v := datain; control_state_v := STATE_CHANGED;
This works in both pre- and post-synthesis simulation and also in real hardware. There is now an 8-bit comparator found for the compare line and no more warning about constant values.
So my question is: Is there a problem with comparing and updating a value in the same state (clock)?
And does the problem als exist for single bit values when used like this:
if my_bit_v = '1' then my_bit_v := '0'; -- do stuff end if;
All inputs to the entity come from other parts in the fpga and are all updated on the same clock. The synthesis report claims the design can run at 58 MHz, actual clock is 50 MHz, no other constraints defined.
The hardware is Xilinx spartan-3e and synthesis is done with ISE9.2.