clockless arbiters on fpgas?

Asynchronous circuits.

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Thanks for posting this!

I should note that this link shows how to use the primitive arbiter-core ("interlock") from the first paper to build a complete arbiter (handshaking, request/grant, etc). The interlock is the box with the funny angle-symbol in figure 3 of the second paper.

Seitz' original paper on building the full arbiter had an error, but I am not aware of any problems with his interlock element.

The following paper claims to prove the correctness of the interlock circuit (see figure 5 for a transistor diagram) under a pretty minimal set of assumptions:

Where correctness means "Because an arbiter cannot be guaranteed to respond correctly in any bounded amount of time, we verify liveness in an almost surely sense -- with probability 1, the arbiter eventually grants some pending request."

Stuff like this turns out to be a pretty big deal, since "interlocks work properly" is one of the very few "timing" assumptions you have to make in delay-insensitive circuits (the other being that certain fanouts are asymmetric and that you know which side has more delay).

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Actually, if you're really curious, here's the poster describing current results (as of April) on Atmel's supurb devices:

Note that I haven't yet built anything that requires an interlock. That's the next step.

- a