CIC filter implementation using FPGA

Hello to all,

I've followed a Hogenauer architecture. Can anyone help me out that what clock frequency should be provided for a 3-ordered CIC decimator, I've used 3 combs and 2 integrator stages in my design alongwith a rate changer.

Thanks, Samia

Reply to
Sam
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First, the CIC usually has the same number of integrator stages as comb stages. The clock frequency, in the absence of clock enables should match the sample rate of the higher side of the CIC (input if it is a decimating CIC, output if it is an interpolating CIC). The reduced rate side typically works on the same clock but using clock enables to control the effective frequency.

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--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Reply to
Ray Andraka

Thanks for your reply. I have used 256 rate changer (i.e. it is of 8bits ), This divided clock will be provided to comb stages. will it be suitable for my design if I provide 44.4khz frequency at the integrator stages. Can you please explain the clock frequency, data rate in detail. Regards, Sam

Reply to
Sam

Thanks for your reply. I have used 256 rate changer (i.e. it is of 8bits ), This divided clock will be provided to comb stages. will it be suitable for my design if I provide 44.4khz frequency at the integrator stages. Can you please explain the clock frequency, data rate in detail. Regards, Sam

Reply to
Sam

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