Re: counter skrews up design

Extraced from a question by alwin

The complete DES pipeline uses the following resources. > > Number of Slices: 1415 out of 1920 73% > Device utilization summary for this counter. > > Number of Slices: 28 out of 1920 1% > > All fine untill I place the counter in front of the pipline. > The result of the synthesis process of the complete design is: > > Number of Slices: 1972 out of 1920 102% (*) > WARNING:Xst:1336 - (*) More than 100% of Device resources are used > > ========================================== > > Am I missing something here? > This is a huge increase of used resources I can't explaine.

As a wild guess, perhaps part of the DES pipeline was being optomized away without the counter there to exercise its full designed functionality? If XST figures out that a bit of logic is never used, or the result never acted upon, then it gets eliminated.

What was taking the counter's place in the synthesis of the pipeline alone? Can you connect the 48 bit count value to IO's (so their value will be unkown to XST) and retry the DES part on it's own?


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Chris Stratton
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Well, maybe it is not the counter causing this problem. The same problems occur when changing other parts of the code (changing # IO's at the top level)

Since this is my first vhdl/fpga project, I need to gain more knowledge about vhdl and synthesis to understand whats going on. And come back later to this board if the problem still exists.

Darn... I 'just can't wait to see my 99 dollar device to crack 250M DES keys/s. (estimated speed..)


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