Regarding the Certificate Program in VLSI Logic Design and Layout Design
TIIT (TTM Institute of Information Technology) in collaboration with
the University Of California at Santa Cruz Extension in the Silicon
Valley and Cadence Design Systems offers a certificate program in
VLSI design engineering.
Students who complete the required courses with minimum grade point average
(GPA) will be awarded a certificate in VLSI design engineering (Physical
Design or Logic Design) from the University Of California Santa Cruz extension
in Silicon Valley.
Transfer your credits: After completion of the course you can transfer12 Credits to your higher studies in USA with the University Of
California at Santa Cruz Extension in the Silicon Valley.
You can also avail Scholarship
Course: Updated Exclusive courses for Layout Design & Logic Design Engineering.
Duration: Will be tentatively for 20 weeks.
Class Timings: Classes will be during the weekends; 6 (20 hours a day)
days Lab will be open to work on Tools.
Placement Statistics: 90% of the people got employed in VLSI Industry
Placement Assistance will be provided, and setting up mock interviews,
resume building, seminar series etc will be provided.
Batches are Starting from : 15th March 2008
BE/BTech/ME/MTech/MSc in either computer science or Electrical/ Electronics
Registrations: Open Online @
You can see:
=B7 VLSI and ASIC Design, Introduction
=B7 VLSI Engineering Fundamentals
=B7 Introduction to IC Manufacturing (Visuals Included)
=B7 Logic Synthesis Principles
=B7 Advanced ASIC Physical Design
=B7 Static Timing Analysis (Tools used: Common Timing Engine)
=B7 System Integrity In SOC design (Tools used: Celtic for Xtalk, VSTORM
for IR drop analysis)
=B7 Demos of live design for all the tools.
=B7 System Verilog
=B7 Introduction to Formal Verification (LEC)
=B7 Introduction unix/shell for VLSI Designers.
The following tools from Cadence will be used for the training:
=B7 SOC Encounter XL, , Incisive Unified Simulator, RTL
=B7 Compiler XL with BG and CTE, Virtuoso XL Layout Editor, Assura DRC/ LVS,
=B7 Assura RC, Virtuoso Schematic Entry.
=B7 Celtic Cross Talk Analysis for Signal Integrity Analysis.
=B7 VoltageStorm IR drop analysis Tools for Signal Integrity Analysis
=B7 NanoRoute Global/Detail Router.
=B7 verilog simulation- NCSim.
=B7 Synthesis - RTL Compiler.
=B7 System Verilog - NCSIM.DFT - RTL Compiler.
=B7 STA- CTE Engine.
Instructors: : Tools are taught by experienced working professionals.
Screening Test: You have to take screening test comprises of basic digital
electronics & Aptitude. Multiple-choice question.
Make sure: Since we will take only 20 Students per batch, we are getting
advance booking for Batches; make sure you will get the seat.
For more info:
TTM Institute of Information Technology (tiit)
Hyderabad12th Square Plaza,
Road # 12,
Hyderabad - 500034,INDIA