Interface Between National Semi Channel Link TX AND Virtex-II

Hello,

I'd like to know if anyone has interfaced a NS Channel Link TX to a Virtex-II FPGA and wouldn't mind sharing their experience. Or, if anyone has any thoughts on this problem. What follows are some details about this situation. There is much I could have added, but to prevent this from being too long, the details are not complete. I hope it's enough to convey the setup and observations.

I'm trying to interface a Xilinx XC2V8000 to a National Semiconductor DS90CR483 using a 12" cable. The parallel data rate is about 68 MHz. The connector and cable are the same as those used on the National Semi's LVDS eval kit. I created an LVDS receiver design in the FPGA to receive the serialized data. I've studied the Xilinx appnotes and verified placement of the LVDS elements in the FPGA, e.g, the DDR registers in the IOBs are used.

The phase shift is close, but not quite where I have predicted, following the NS datasheet and considering the small, if any, internal FPGA skew between the clock path and data paths to the DDR registers. The "error" is "measured" by observing the parallel data output from the LVDS receiver modules. The phase shift was empirically adjusted to center the clock in the middle of the "no error zone." The "no error zone" can actually have errors sometimes (more on this in the next paragraph).

At 60 MHz, the errors are fewer. When the cable is longer, e.g. 3-4 ft, the errors are fewer. Also, some links seem to have more errors than others. (Changing cables does not appear to affect this much.) Resetting the FPGA DCM does not correlate well to the errors. Powering up/down the system does seem to affect the errors. The errors include times when no clock is output from the DCM.

Thank you for any thoughts, Mark

Reply to
Mark
Loading thread data ...

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.