"Cannot synthesize logic..." ERROR

I think the problem happens due to to the same register being clocked by different events - that's what the compiler does not like. What would you suggest ?

I think maybe to have another process which sets RISING_FLAG to 1 at rising edge and FALLING_FLAG to 1 at falling edge. Then make my other process sensitive to the flags instead of clock.

process(clock, reset) begin if reset = '1' then --reset flags elsif rising_edge(clock) then RISING_FLAG

The FPGA (and most of the world) doesn't have flip flops that clock on both edges, so what hardware do you expect the synthesizer to map to? You should not use a synthesis tool if you don't understand what the hardware will look like.

Anyway, one possible fix would be to generate a double-rate clock with a PLL (Are you using Stratix?). Then you can clock everything on rising edge but use enables on alternating clocks to act like your code. Oh, you also have a typo - you have rising_edge(clock) but falling_edge(clk), so it thinks you have two different clocks.

David

You could try using a DDR type register, if available in your target device. Not sure if they can be inferred or whether they'd have to be explicitly instanced. I'd say most probably the latter...

That does sound like what you're after, though I'm not sure how the synthesis would handle to two different signal assignments to it, I guess it could use multiplexers though I wonder about setup and/or hold timings in this situation.

Thank you, I'll think how I should go around it

To test this code, I am using a lower-end cheap and old FPGA (apex II).

Thank you, I'll think how I should go around it

To test this code, I am using a lower-end cheap and old FPGA (apex II).

How about using two separate 32-bit registers, reg1 and reg2, instead of reg(1) and reg(2). You need to use 2 processes. The process for reg1 would use the rising edge of the clock, and the process for reg2 would use the falling edge of the clock.

-Dave