Interfacing SJA1000 to ISA bus

ISA bus has ALE signal, it is pin B28.

Vadim

Thank's for your answer. Do you know where i can find ISA ALE signal timing diagram on the net (or, better, complete isa timing diadrams)? Thank's in advance

Massimo

But are address/data multiplexed?

-- Grant Edwards grante Yow! My nose feels like a at bad Ronald Reagan movie... visi.com

Google. Search for "isa bus timing" - plenty of links.

HTH, Vadim

Yes, SJA1000 multiplex address and data;

I solved the problem reserving 2 specific address inPC io space: one for address and one for data: when the pc data bus contain address for SJA1000 i haven't to generate rd/wr signals (and this isn't a problem), but i have to generate AEN used by the SJA1000 to catch the address, and thats's the problem!; When the pc data bus contain data for SJA1000 i have to generate rd/wr signals (this isn't a problem), ant at the end or the read/write cycle i have to rise up AEN I think that is'n possible use ISA ALE signal because i think that this line switch on every I/O cycle.Is it correct?

Thank's

Massimo

AFAIR, no (I touched ISA stuff the last time 13 years ago). Sorry, non't have working examples at hand, but interfacing was quite straightforward.

Vadim

ISA address/data are not multiplexed, SJA1000 yes

Massimo

I meant ISA. IIRC, they aren't. If you wanted to access the SJA transparantly (using normal read/write or input/output), you'd have to design a state-machine that does the address/data multiplexing and generates the ALE and RD/WR signals.

It's not possible to use it directly without some other octal buffers and some stateful logic.

Yes, i work on it with, but i post a question to the newsgroup to see if anyone have yet made it and can help me...if there is an application note or a tutorial on the net...

thank's

Massimo

Yes, the ALE signal is actually the same signal as generated by the x86 CPU even though it no longer comes from the CPU. The ISA bus is simply the CPU address and data demultiplexed along with some decoded timing strobes.

Your interface will need to be a mux to remultiplex the address and data and then you will need to regenrate some timing because the ALE will not be what you need to feed into the SJA1000. This is because you need to hold the address beyond the falling edge of the ALE. So either generate an earlier ALE or delay the mux control. Or regenerate all of it yourself in a PLD.

I recommend that you get the book "AT Bus Design" by Solari. For all practical purposes this is the ISA bus spec.