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Connecting Intel 386EX to External Device

Respected Experts, In the given figure assume one box as Intel 386EX embedded processor and the other one as external device(eg: memory).

Intel 386EX processor External decice(eg:memory) .------------. .-------------. . . . . . W/r#. . . . . . . . rd# .------------ .rd# . . wr# .------------ .wr# . . . . . .------------. .-------------. The rd# of processor is connected to rd# of external device. The wr# of processor is connected to wr# of external device.

Intel has provided 3 pins on chip .i.e. w/r#, rd#, wr# for controlling of read and write cycle.

1) what is the purpose of providing 2 sets of control signals.i.e. w/r# and rd#, wr#.

2) Is there any significance of w/r#.

3) Which is the better way of connecting 386EX to external device.

4) who controls these 3 pins. Is it possible to control these pins by the user.

5) what happens if w/r# is left floating. 6) We suspect some timing problem in read and write cycle, so is it necessary to make rd# and wr# as a function of w/r# to avoid timing problems.

With regards Ravi Kumar.N

Reply to
Ravi kumar.N
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rd# and wr# are the simple signals that normally can be directly connected to the external device, together with a chip select. w/r#, together with d/c#, m/io#, refresh#, and ads#, specify the full cycle type (interrupt ack, io read, io write, memory code read, halt, refresh, memory data read, or memory data write. These signals are necessary if you want to use pipelined address mode. Pipelined address mode requires external logic that decodes these signals.

In cases where rd#, wr# and a chip select are fast enough, they are the easiest way. The method is fine for I/O devices. For memory, this method is also fine if you either have a very fast memory (~12 ns), or can afford a few wait states. For memory where you must run with 0 wait states and have 70 ns RAM, you have to use pipelined address mode, which requires external logic that decodes w/r#, d/c#, m/io#, and ads#, and controls na# and ready#. You also require address latches on the address bus. In that case, you don't need rd# and wr#. Pipelined address mode isn't very well described in the manual. It is described better in the 386SX manual.

The CPU controls them all, except when an external bus master takes over the whole bus using HOLD/HOLDA.

Nothing, it is an output from the CPU.

Karl Olsen

Reply to
Karl Olsen

Hi karl

thanks for your response.

Actually i have interfaced a cfcard with 386EX. The schematic is like this. It is Interfaced in memory mapped I/O fashion.

Intel 386EX CFCARD -------------- A0-A10 -------------- . An. -------------------->.An . . . D15 --- D0 . . . Dn. -------------------->.Dn . . . . . . P3.5,3.6 . . CE1#,CE2# . . . . . . RD#. -------------------->.RD# . . . . . . WR#.--------------------->. WR# . . . . . . RESET .--------------------->.RESET . . . . . . P3.0.--------------------->.REG# . . . . . . P3.1.

Reply to
Ravi kumar.N

The thing that stands out is that you are ignoring all address lines above A10. If you are memory mapping you have to restrict the access to some area of address space.

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Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net)
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