Fast NPN/PNP transistors for a totempole driver

Hi

I have a 74HCT14 hex inverter driving a NPN/PNP (BC847/BC857) totempole stage connected to GND and 5V

The output is a small capacitor connected from the common node to ground

The bottom PNP transistor has a current sense resistor to ground so I can measure the current when the output falls from 5V to zero

My problem is I want to drive the totempole with about 10ns tr/tf and this causes an error current in the PNP transistor due to BE parasitic capacitances

So I need a couple of fast transistors - better than the BC857 with regards to capacitance and ft and it needs to be affordable. Anyone got a direct hit?

Regards

Klaus

Reply to
Klaus Kragelund
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Reply to
bill.sloman

Hi Klaus,

I would test 74ACT14.

Marte

Reply to
Marte Schwarz

Yep. Or even parallel a few inveters for more current, all depending on how heavy the load is.

James Arthur

Reply to
dagmargoodboat

I did infact look at the ACT devices, but could not right away find info if its ok to parallel them since the device is a schmitt trigger and a slow changing input voltage would lead to much "cross" conduction between devices. Ofcourse I could use one device to sharpen the input edge and run the others off this first inverter. Is it ok to parallel if the cross conduction period is small (perhaps with output resistors on all outputs)?

Moreover I read one this group a while ago about a special part rated for high currents (perhaps it was a 4000 series chip). I have searched but could not find the thread......

Would it be possible to use another coupling to get the speed and low parasitic capacitance I'm after? And still being able to measure by means of a current sense resistor the transient current in an unknown capacitor?

Regards

Klaus

Reply to
Klaus Vestergaard Kragelund

Yes, you can parallel them, and yes, you can expect them to cross-conduct for a fraction of a nS, drawing a nasty spike. It's not destructive though, so you just bypass and ground accordingly, or add current-sharing resistors if you really care.

Squaring up the waveform with a preliminary inverter is a good idea, and I'd square it up with something before the 'ACT14, personally. I don't know about the 'ACT14 in particular, but I've seen grossly excessive dissipation in earlier devices when fed slow waveforms.

Another possiblity is using a MOSFET gate driver. Those are basically very hefty CMOS inverters, some including bipolar buffers on their outputs. I've got some TPSxxxx devices from T.I. fitting that description.

Cheers, James Arthur

Reply to
dagmargoodboat

Take a look at the schematic of the "standard" NPN/NPN totempole output used in the 74xx series of logic. There is a short period of time (up to 6nSec) when both the top and bottom NPNs conduct, creating the "sharp spike" that others mentioned elsewhere in this thread. That happens when the bottom NPN is supposed to turn off, and the top NPN is turned on. That happens *not* due to B-E capacitance that you refer to, but to stored charge in the base that must be removed for the NPN to turn off. Perhaps a similar problem exists inyour (discree?) circuit. The solution to the NPN/NPN totem pole problem is to 1) put a resistor in series with the base of that bottom NPN, and 2) add a PNP with its emitter connected to the NPN base and its base to the "input" end of the resistor. When the driver turns off, the PNP turns on and pulls the base charge out. This scheme can speed up the output from 2 to 5nSec and will completely eliminate the spike at most temperatures (in an IC, the spike is reduced by only a few orders of magnitude at 125C).

Reply to
Robert Baer

Klaus, forget TTL, it was never designed to cope with 100MHz. Have a look at other families. What kind of voltage range on the output is required and what is the load.

Rene

Reply to
Rene Tschaggelar

The output load from the totempole point of view is >300Ohm and max

100pF

5V or any other voltage will be fine

Regards

Klaus

Reply to
Klaus Kragelund

100pF raised 5 volts in 10nS will take 50mA, a very modest requirement. Paralleled 74ACxxxx CMOS gates will do the job quite easily, and make pretty rail-to-rail squarewaves too.

Even the 74HCxxxx types might do--a single 74HC244 is guaranteed to drive 50pF in 12nS--but you'd need to parallel more gates than with the newer stuff.

Regards, James Arthur

Reply to
dagmargoodboat

I tend to use the 74F0037, a quad NAND driver with 30 Ohms output impedance. It rises to 2.5V in 2ns then becomes slower, say another

4ns to 4V, all into 50 Ohms.

Then these are MOS driversfrom various manufacturers.

Rene

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& commercial newsgroups - http://www.talkto.net
Reply to
Rene Tschaggelar

In article , wrote: [....]

If you want faster edges, you can run the thing on 5.5V. They get a bit faster as you go up from the STD 5V supply.

--
--
kensmith@rahul.net   forging knowledge
Reply to
Ken Smith

I think this thread has gone astray. The OP wanted to measure load current, which was being obscured by totem-pole device capacitive currents.

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
     It\'s what you learn, after you know it all, that counts.
Reply to
Jim Thompson

In article , Jim Thompson wrote: [....]

Not astray just digressing wildly.

--
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kensmith@rahul.net   forging knowledge
Reply to
Ken Smith

Hmm... I took the OP's current-sense resistor to be for troubleshooting, but you could be right Jim.

No worries, just move the sense resistor to the CMOS gate's Vss. Be sure to feed the CMOS driver-part fast edges though, and/or use a non-inverting part to avoid negative-feedback via Vss & such. (a small Vss resistor + output resistor adds a little input hysteresis to an ordinary, non-inverting CMOS gate.)

I suggested paralleling CMOS gates because the OP indicated he's already using one as the driver.

Cheers, James Arthur

Reply to
dagmargoodboat

Excuse me...but a PNP/NPN combo is not a "totempole." Who the hell knows what this person is asking? I hope he communicates to himself better than this- he will be stuck forever.

[snip]
Reply to
Fred Bloggs

Yeah, you're right, it's not what we normally mean by 'totem pole,' but from this:

"The bottom PNP transistor has a current sense resistor to ground so I can measure the current when the output falls from 5V to zero "

I took the OP to mean this:

. Vcc . -+- . | . | . |/ Q1 . +---| BC847 . | |>. . | | . | o----> >---o----+ . |\\ | | | | . | \\ | |

Reply to
dagmargoodboat

Right. Whereas a totem pole is this:

Reply to
Winfield Hill

Yes, and this was infact my first solution back when I did tests with the CD4093 chip and it failed from sufficient output drive/speed

Regards

Klaus

Reply to
Klaus Vestergaard Kragelund

100% correct :-)

Regards

Klaus

Reply to
Klaus Vestergaard Kragelund

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