Thanks to all who have posted here, I have read all of the helpful information pointed out on the Xilinx site. Very interesting, and has made me rethink my coding style significantly with regards to the reset signal.
Jason
Async reset
Oct 20, 2004
21 Replies
I have seen warning messages from
Quartus synthesis will take advantage of registers which do not specify a power-up condition in don't care optimizations. Note that this can often result in registers being synthesized away because they are stuck-at in one power-up state, so it is important for designers to read the messages as warnings, not info. The assignment editor allows one to protect a register from this optimization, or specifically give a power-up value to a register or set of registers.
Hope this helps.
- Subroto Datta Altera Corp.
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