Current synthesis pretty much only instantiates the SRL16 as a fixed length shift register, and then only if the designer didn't put resets on the registers. There is supposedly a magic incantation in Synplicity that will infer a dynamic shift, but for th elife of me I have not been able to get it to infer that consistently, and the words to the incantation seem to change with each revision of the software. I find it to require less effort just to instantiate the SRL16, especially if you are actually using the dynamic capability. Also, a common mistake with inferred fixed length shift registers is the synthesis often does not infer a flip-flop at the SRL16 outputs, which kills clock performance. Synplify will put a flip-flop at the output of a delay, but if you have a register deeper than 17 clocks, it strings together SLR16's with no flip-flops between, which again kills the performance. (This may have been fixed in later versions, I haven't checked).