Anybody understand this ISE 7.1 error, and what to do about it???

Current synthesis pretty much only instantiates the SRL16 as a fixed length shift register, and then only if the designer didn't put resets on the registers. There is supposedly a magic incantation in Synplicity that will infer a dynamic shift, but for th elife of me I have not been able to get it to infer that consistently, and the words to the incantation seem to change with each revision of the software. I find it to require less effort just to instantiate the SRL16, especially if you are actually using the dynamic capability. Also, a common mistake with inferred fixed length shift registers is the synthesis often does not infer a flip-flop at the SRL16 outputs, which kills clock performance. Synplify will put a flip-flop at the output of a delay, but if you have a register deeper than 17 clocks, it strings together SLR16's with no flip-flops between, which again kills the performance. (This may have been fixed in later versions, I haven't checked).

Finally got to the heart of the problem. Apparently when porting xco files over to a project for a new device (in this case V4) there is a problem that ISE 7.1 will not upgrade the core to current settings with the new device. This apparently happens even when the logicore is the same version (multiplier in this case). The logicore has to be rebuilt and hence the proper construction for the V4 follows.

Thanks for all your help!!

-Andrew