ModelSim

modelsim isn't really that difficult to use... its the VHDL or verilog testbench that's the bugger.

Simon

It comes with quite a good introductory tutorial.

Leon

Yeah. I am gathering that. And it is also difficult to understand where VHDL testbenches "begins" and the other takes over. There is also a waveformer in the Xilinx tool that is somewhat intuitive. I have found some text books that cover simulation testbenches and give a few examples. Very week though in terms of the numbers of examples and the strategy behind the use of the various commands. I still haven't found an example of a bidirectional test bench. I also started searching the web with the words downto and testbench and have found some examples, but these are not what I would call good tutorials.

The 58 page one?

The design entity becomes an instance in the testbench architecture.

The basic strategy is to wiggle the inputs and watch for expected values on the outputs.

here's one:

Good luck.

-- Mike Treseler

Personally, I find a VHDL testbench much easier to write than generating a waveform type stimulus. In VHDL I can write procedures to control a bus interface reading data from a file or provide feedback from one external interface to another. In short, it is a lot like writing any other program since it does not need to be sythesizable.

The *hard* part is knowing what you want it to do!

--
Rick "rickman" Collins

rick.collins@XYarius.com

IIRC the book "VHDL for Logic Synthesis" by Rushton has a good section on writing VHDL testbenches, talks about file IO and so on.

My preferred approach, when possible/sensible, is to write fairly generic VHDL testbenches that read the stimulus and expected response data from text files, and then drives the unit-under-test from that data. This lets you use other tools to generate the input and output datasets. I've used this to verify implementations of image processing algorithms - prototype the algorithm in matlab, design the hardware, then drive both the matlab and VHDL models with the same input data files, comparing the results.

Rgds,

John

This sounds like a powerful way to really check the video processing. What kind of video processing are you doing? And what do the VHDL models look like?

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Hi Brad,

Brad Smallridge wrote:

I'm sure it could be more powerful, but it met my needs. I'm not doing a lot of video/image work now, this is from a few years ago when I was investigating some real-time remote sensing / image processing algorithms.

I've attached a sample test bench, maybe it will be useful in showing you the overall structure and file IO. It's not particularly sophisticated, but will give the general idea..

Regards,

John