OCXOs are getting cheap

Where can I get a ready-made 32768 oscillator module with a logic output (G-job)? ...Jim Thompson

-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

| 1962 | I love to cook with wine. Sometimes I even put it in the food.

Digikey should have lots of them.

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John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

Nice. Datasheet link?

Cheers

Phil Hobbs

ConWin BOC11003V-010.0M.

Decent, but not amazing, phase noise, about what you'd expect for a cheapish DIP oscillator.

I'm thinking about a new timing box. The FPGA could be clocked, roughly 100 MHz, by a cheap programmable VCXO, like one of those Xpresso things. The DIP OCXO could be a plug-in option. If the FPGA sees the 10 MHz from the OCXO, it would lock the cheap oscillator to that. Then, if the customer gives us an external 10 MHz, we would lock one or maybe both XOs to that.

I'm in one of those numerical-wasteland situations, dealing with selecting UHF oscillator frequencies, VCXO frequencies, OCXO frequency (probably 10 MHz), equivalent-time sampling ratios, divisors, pull ranges, TCs, a real numeric nightmare. Luckily, I don't have to understand it, I only need to come up with one set of numbers that works. Or better yet, delegate it.

Or let yourself think about Direct Digital Synthesis with one of the fancie r chips you could buy from Analog Devices, or fake up for yourself in your FPGA. That gets you out of numerical wasteland, because the DAC in the DDC saves you from having to deal with integer-only arithmetic.

You've got to low-pass filter the DAC output, but that isn't rocket science .

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Bill Sloman, Sydney

I'm in one of those numerical-wasteland situations, dealing with selecting UHF oscillator frequencies, VCXO frequencies, OCXO frequency (probably 10 MHz), equivalent-time sampling ratios, divisors, pull ranges, TCs, a real numeric nightmare.

That's the fun part. ;)

I've been building PLLs for thirty-odd years, and they're still magic. (not black magic any more, but still magic.)

Cheers

Phil Hobbs

This one involves what is essentially equivalent-time sampling of one oscillator's waveform, via an ADC that has another, different clock. The list of candidate fractional frequency ratios that might work is enormous. The FPGA will have to sort out what the resulting mess of samples actually means.

This is NOT the fun part! Yes, there is a solution. No, I don't want to find it.

DDS isn't so hard. I did an analysis a while back and found that the problem with most DDS chips is the phase noise introduced by truncation of the phase word. That gives these chips close in phase noise which is hard to filter. However, in an FPGA, or even a processor driven DDS if lower frequencies are being used, there are other ways to calculate the DAC word than a look up table which limits the size of the phase input. A 20 bit phase word can be used with a 20 bit DAC word to give a very high spur free range. If the DAC has more limited bit width, truncation here does not produce so many close in spurs and dither can be used to spread the ones present.

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Rick

Do you mean you'd prefer it to remain undiscovered - until one of your rivals gets into the act? Or do you mean that you'd prefer that one of your minions discovered it for you?

I used to have delusions about about launching junior engineers at messy problems, but found that it didn't actually work - they'd just get stuck and need so much hand-holding that it was quicker to do it myself.

Senior engineers were a lot more effective, but negotiating one of them into solving one of my problems was quite a bit trickier. First you had to make the problem "our problem" ....

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Bill Sloman, Sydney