We're planning a new universal boot loader for a family of ST processors. The uP would host the loader in a bit of local flash and read an outboard serial flash to get the specific application code and one or more FPGA configurations.
So, how many config bits might there be for a modern mid-range FPGA doing a moderately complex application?
I think we could enable compression too.
Please consider this a PHB type question. I don't do FPGA development myself, past whiteboarding.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Am 08.11.19 um 20:08 schrieb John Larkin:
The size of the programming file is in the data sheet. It is constant and does not depend on the implemented circuitry.
Newer FPGAs may allow to program only some sectors of the chip.
regards, Gerhard
Anyone know what a "PHB" type question is?
-- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
I've never used compression on the bit stream, but I recall there is compre ssion available, possibly even through the tools. I don't have any direct work experience with this, but I have a recollection that most of the bits in an FPGA bit stream are zeros. So some type of a RLL compression may be very useful.
Where have you seen info on programming only parts of chips? I recall some years back Xilinx talked about partial configuration, but they never got t hat working to the point it was generally available. I think they worked o n it for a few large customers and they likely decided it wasn't worth the effort.
Now, instead of programming a part of an FPGA for different tasks, you can easily just use multiple FPGAs and program them individually. Lattice make s some very tiny FPGA packages. I mean cell phone tiny.
-- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209
Page 21:
d
ression available, possibly even through the tools. I don't have any direc t work experience with this, but I have a recollection that most of the bit s in an FPGA bit stream are zeros. So some type of a RLL compression may b e very useful.
the bitstream can make the bit file much smaller depending on how much you use of the fpga, but if you decide to encrypt the bitstream and put a key i n the fpga you are back at the maximum size
I was just wondering what sort of config file sizes people were really seeing. Maybe compressed, too.
Looks like a 1 or 2 Gbit serial flash is cheap nowadays. I can imagine storing maybe four configs in the flash chip.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
fredag den 8. november 2019 kl. 21.20.55 UTC+1 skrev John Larkin:
The uncompressed FPGA configuration file size does not change with the device utilization. You need to look at the data sheet for the particular device. Obviously the compressed file size will be variable - with anything from
0% to near 100% compression ratio dependent on content and compression algorithm.
Interesting, but looks like overkill for a little resident boot loader.
We have used SD cards with Zynq chips, but they already know how to boot from SD.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Pointy-Haired Boss, a character from the Dilbert cartoon. The theme of the cartoon is workplace relations.
Jeroen Belleman
Sloman is the model for the 'Wally' character?
No wonder a Google search didn't find anything. Just the reference is obscure enough, using an abbreviation makes it local jargon.
-- Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209
I think we are well past the point where a reference to PHB can be considered obscure in engineering circles
-- Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209
The built-in bitstream compression merely reuses indentical configuration frames. This gives good results on an empty FPGA, but poor results on a moderately utilised one.
We use gzip -9 here. From this thread on the Xilinx forum,
Regards, Allan
From Lattice ECP5 sysCONFIG Usage Guide FPGA-TN-02039.
LFE5-45 - 8.86Mb
From Xilinx UG470 Xilinx Artix 35T and 50T need the same 17.536 Mb
MK
Why complicate things with memory soooo cheap ??? Just store raw data...
I did a little compression thing, file compressor in PowerBasic and unpacker in assembly, based on finding runs of 1s or 0s. Typical compression was 2:1 or better, and the decoder was small and very fast. It configured most FPGAs faster than the un-compressed version, because the 1-or-0 unpack bursts were the tightest possible loops.
I wouldn't use that again, because an ARM with hardware SPI or QSPI interfaces, from serial flash and to the FPGA config pins, would probably be faster.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Compression could save bootup time. The Artix7 that I'm using now is only 17 mbits, but some of the Vertix chips are approaching a gigabit. Luckily, I can't afford them.
Probably lots of config bits.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.