We're planning a new universal boot loader for a family of ST processors. The uP would host the loader in a bit of local flash and read an outboard serial flash to get the specific application code and one or more FPGA configurations.
So, how many config bits might there be for a modern mid-range FPGA doing a moderately complex application?
I think we could enable compression too.
Please consider this a PHB type question. I don't do FPGA development myself, past whiteboarding.