(rise/fall)register, and one for a mux controlled by the clock level. You have to either use opposite edges of the same clock signal, or use two clocks from the same DCM that are 180 degrees apart in phase. As with most things in the reference manual, they often support additional means (e.g. a single process with two clocks or both edges of one clock, mutually exclusive, as specified in
1076.6). I know they support dual-edged processes in which the same signal/variable is not assigned on both edges, so I suppose you could do it in at most two, if not a single process (using variables for the registers and a mux assignment to the output signal after the last "end if":know if the 1076.6 method works or not (including a double-edge process with assignments on both edges to the same output signal). Note that synplify does not support inferrence for all target architectures that have DDR output registers.
I'm sure there's many ways to describe this in a single process in VHDL, I was sondering what the Verilog template looked like (since the thread started off on that vein).
For VHDL I could see a single process without variables like:
process (rst, clk1, clk2) is begin if rst then ouput