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A small clock synchronization challenge with Virtex E

Greetings, this is my first posting to this group, but I've been following the discussions for some time.

I have a small problem which I'm trying to solve:

My design has a Virtex E, and I need to generate a 1MHz clock and a

4MHz clock from a single clock source. The are to be used internally and they need to be synchronized. My problem is that the CLKDLLE primitive needs a CLKIN of at least 25MHz. I can supply that, I have an external oscillator tunable from 0 (or very low at least) to 40MHz. But the CLKDLLE can divide by 16 at maximum, thus I cannot use it to create the 1MHz clock.

Do I have any options? Are there any other techniques I may apply to perform division and get a minimal clock skew between the two clocks?

What would happen if I tried to use a CLKIN of 16MHz? No DLL lock?

Thank you,

-Geir Botterli

Reply to
Geir Botterli
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Use a single clock for the FPGA. Use enables to clock the 4 MHz flops and/or the 1 MHz flops at every nth (or

4*n-th) edge. One simple clock. No DLL. All flops synchronous with no skew. Apply the multi-cycle constraint through the enables to get your timing at 4 MHz or 1 MHz. A thing of beauty.

Reply to
John_H

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Reply to
Ray Andraka

I'm afraid I don't get how I should use clock enables to achieve this. The only "solution" i have come up with is like this:

always @ (posedge clk_4MHz) clk_2MHz

Reply to
Geir Botterli

Here is an example of how to use "clock enables".

The example uses one of the count states as the "emable" Variable a will be updated every 4th 4Mhz clock (at a 1Mhz interval).

always @ (posedge 4Mhz) begin cnt[1:0]

(or

at 4

Reply to
Mike Lewis

damn typo ... that should be "else a

Reply to
Mike Lewis

Reply to
Geir Botterli

You don't use an else for clock enables, here is cleaner version of the above.

reg [1:0] cnt; reg ce;

always@(posedge 4mhz) begin cnt

Reply to
B. Joshua Rosen

Re: your title...."Challenges" are for managers and manger wanna-bes who have been taught that "problem" is a four letter word. Problems are solved by engineers.

Does the Virtex E have a DCM?

Anyway, as somebody else pointed out, use enables (which end up in the combinatorial logic of your D inputs).

if(clk'event and clk='1') then if(slow_en='1') then q Greetings, this is my first posting to this group, but I've been

Reply to
William Wallace

Greetings, Geir.

(or

...

If you have a 20 MHz clock but you want a 4 MHz counter and a 1 MHz counter, you need to generate enables that are active every 5th and every 20th master clocks. The counters themselves effectively "run" at 20 MHz in this case but the enables slow that all down. You then need to look at how to apply multi-cycle constraints to tell the place & route tools that all registers fed by "div5" only need a 4MHz cycle time and the "div20" fed registers need

1 MHz timing constraints. Only the divide signals need to run at 20 MHz.

reg [2:0] div5cnt; reg [1:0] div20cnt; reg div5,div20; always @(posedge Clk20) if( div5cnt == 3'h4 ) begin div5cnt

Reply to
John_H

Thanks to all that replied; I hope to contribute back to this group some day :)

-Geir

Reply to
Geir Botterli

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